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MI325X PLATFORM (AMD)
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| Process Node | 5nm FinFET / 6nm FinFET |
|---|---|
| Tdp W | 1000 |
| Peak Engine Clock Mhz | 2100 |
| Gpu Compute Units | 2432 |
| Architecture | CDNA |
| Gpu Memory Gb | 256 |
| Interconnect | 7x 128 GB/s per GPU |
| Memory Bus Width Bits | 8192 |
| Accelerator Form Factor | OAM |
| Memory Type | HBM3E |
| Amd Infinity Cache Last Level | |
| Document Type | |
| Matrix Cores | |
| Media Engines | |
| Product Name | |
| Ras Features | |
| Software Platform |
| Sr Iov Support |
|---|
| Stream Processors |
|---|
| System Total Memory Gb |
|---|
| SKU | MI325X PLATFORM |
|---|
| Tagline | |
|---|---|
| Positioning | |
| Peak theoretical FP8 with sparsity performance | |
| Baseboard standard | |
| Number of accelerators per platform | |
| Total HBM3E memory | |
| Host I/O connections | |
| Compatibility | |
| AI peak theoretical performance — TF32 | |
| AI peak theoretical performance — FP16 | |
| AI peak theoretical performance — BFLOAT16 | |
| AI peak theoretical performance — INT8 | |
| AI peak theoretical performance — FP8 | |
| HPC peak theoretical performance — FP64 vector | |
| HPC peak theoretical performance — FP32 vector | |
| HPC peak theoretical performance — FP64 matrix | |
| HPC peak theoretical performance — FP32 matrix | |
| Active interposer dies (AIDs) | |
| Memory bandwidth | |
| Memory clock | |
| Ring of 8 aggregate bandwidth | |
| Scale-out network bandwidth | |
| Supported low-precision data types | |
| Model scale capability | |
| Baseboard description | |
| Inter-GPU link bandwidth | |
| Links per MI325X | |
| HBM3E memory per module | |
| GPU architecture detail | |
| Coherent shared memory | |
| Peak bandwidth within each GPU accelerator | |
| Bidirectional Infinity Fabric bandwidth between GPUs | |
| Peak aggregate bandwidth | |
| Infinity Cache shared | |
| Supported AI & ML frameworks | |
| Supported LLM ecosystems | |
| Diagram — module memory | |
| Diagram — interconnect | |
| Diagram — I/O connectivity | |
| Copyright |
