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MI300A (AMD)
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| Process Node | 5nm FinFET |
|---|---|
| Peak Engine Clock Mhz | 2100 |
| Gpu Compute Units | 228 |
| Architecture | CDNA 3 |
| Gpu Memory Gb | 128 |
| Fp16 Bf16 Tflops Dense | 980.6 |
| Memory Bandwidth Tb S | 5.3 |
| Fp8 Tflops Dense | 1961.2 |
| Interconnect | 4 x16 (128 GB/s) |
| Fp32 Tflops | 122.6 |
| Int8 Tops Dense | 1961.2 |
| Memory Bus Width Bits | 8192 |
| Tdp W | 550 |
| Memory Type | HBM3 |
| Fp16 Bf16 Tflops Sparse | 1961.2 |
| Amd Infinity Cache Last Level | |
| Fp64 Tflops | |
| Fp8 Tflops Sparse | |
| Int8 Tops Sparse | |
| Matrix Cores | |
| Media Engines |
| Product Name |
|---|
| Ras Features |
|---|
| Software Platform |
|---|
| Sr Iov Support |
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| Stream Processors |
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| Supported Data Types |
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| Tf32 Tflops Dense |
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| Tf32 Tflops Sparse |
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| SKU | MI300A |
|---|
| Product type / description | |
|---|---|
| Infinity architecture generation | |
| TF32 matrix | |
| Video codec acceleration footnote | |
| Form factor | |
| I/O Dies (IODs) | |
| AMD ‘Zen 4’ x86 CPU cores | |
| Memory clock | |
| Scale-out assignable PCIe® Gen 5 or Infinity Fabric Links | |
| Scale-out network bandwidth | |
| Maximum TDP | |
| Virtualization partitions | |
| x86 ‘Zen 4’ cores (chiplet breakdown) | |
| Accelerated compute dies (XCDs) | |
| L1 cache per CU | |
| L2 cache shared across CUs | |
| AMD Infinity Cache shared between XCDs and CPUs | |
| HBM3 memory (coherent shared) | |
| On-package peak throughput | |
| Decoders (architecture detail) | |
| SR-IOV partition memory | |
| Bidirectional connectivity per APU | |
| Infinity Fabric interface assignment | |
| Peer-to-peer connectivity (4-APU config) | |
| External I/O connectivity (4-APU config) | |
| Storage interfaces | |
| USB interfaces | |
| Supported AI & ML frameworks | |
| Copyright / trademark notice |
