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HMCG84MEBRAXXXN (SK hynix)
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| Speed Mt S | 4800 |
|---|---|
| Capacity Gb | 32 |
| Rank Organization | 32GB (1Rx4) |
| Memory Class | rdimm |
| Height Mm | 30.75 |
| Die Density Gb | 16 |
| Registered | true |
| Memory Generation | ddr5 |
| Ecc | On-Die ECC |
| Product Name | DDR5 SDRAM RDIMM Based on 16Gb M-die |
| Pin Count | 288 |
| Voltage Vdd V | 1.1 |
| Act To Pre Command Period Tras Max | |
| Act To Pre Command Period Tras Min | |
| Bank Address In A Bg | |
| Bg Address | |
| Cas Latency | |
| Cl Nrcd Nrp | |
| Cl Trcd Trp |
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| Column Address |
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| Component Composition |
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| Corner Radius |
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| Ct Mode Ronpd Ct Vobdc 0 2xvddq Max |
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| Ct Mode Ronpd Ct Vohdc 0 95xvddq Max |
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| Ct Mode Ronpd Ct Voldc 0 5xvddq Max |
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| Ct Mode Ronpd Ct Vomdc 0 8xvddq Max |
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| Die Type |
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| Document Revision |
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| General Tolerance Note |
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| Grade |
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| Idd0 |
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| Idd0f |
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| Idd2n |
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| Idd2p |
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| Idd3n |
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| Idd3p |
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| Idd4r |
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| Idd4w |
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| Idd5 |
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| Idd5b |
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| Idd5c |
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| Idd6n |
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| Idd7 |
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| Idd8 |
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| Module Description |
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| Of Bank Groups |
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| Of Ranks |
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| On Die Ecc |
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| Pin Number Callout |
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| Product Type |
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| Row Address |
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| Tck |
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| Tras |
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| Trc |
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| Trcd |
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| Trp |
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| Units |
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| Vddq |
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| Voltage Vpp V |
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| SKU | HMCG84MEBRAXXXN |
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| Base Die | |
|---|---|
| DRAM VDD/VDDQ | |
| DRAM VPP | |
| Organization | |
| Page size | |
| RON34Pd, VOLdc=0.5*VDDQ, Min | |
| RON34Pd, VOLdc=0.5*VDDQ, Nom | |
| RON34Pd, VOLdc=0.5*VDDQ, Max | |
| RON34Pd, VOMdc=0.8*VDDQ, Min | |
| RON34Pd, VOMdc=0.8*VDDQ, Nom | |
| RON34Pd, VOMdc=0.8*VDDQ, Max | |
| RON34Pd, VOHdc=0.95*VDDQ, Min | |
| RON34Pd, VOHdc=0.95*VDDQ, Nom | |
| RON34Pd, VOHdc=0.95*VDDQ, Max | |
| RON34Pu, VOLdc=0.5*VDDQ, Min | |
| RON34Pu, VOLdc=0.5*VDDQ, Nom | |
| RON34Pu, VOLdc=0.5*VDDQ, Max | |
| RON34Pu, VOMdc=0.8*VDDQ, Min | |
| RON34Pu, VOMdc=0.8*VDDQ, Nom | |
| RON34Pu, VOMdc=0.8*VDDQ, Max | |
| RON34Pu, VOHdc=0.95*VDDQ, Min | |
| RON34Pu, VOHdc=0.95*VDDQ, Nom | |
| RON34Pu, VOHdc=0.95*VDDQ, Max | |
| RON48Pd, VOLdc=0.5*VDDQ, Min | |
| RON48Pd, VOLdc=0.5*VDDQ, Nom | |
| RON48Pd, VOLdc=0.5*VDDQ, Max | |
| RON48Pd, VOMdc=0.8*VDDQ, Min | |
| RON48Pd, VOMdc=0.8*VDDQ, Nom | |
| RON48Pd, VOMdc=0.8*VDDQ, Max | |
| RON48Pd, VOHdc=0.95*VDDQ, Min | |
| RON48Pd, VOHdc=0.95*VDDQ, Nom | |
| RON48Pd, VOHdc=0.95*VDDQ, Max | |
| RON48Pu, VOLdc=0.5*VDDQ, Min | |
| RON48Pu, VOLdc=0.5*VDDQ, Nom | |
| RON48Pu, VOLdc=0.5*VDDQ, Max | |
| RON48Pu, VOMdc=0.8*VDDQ, Min | |
| RON48Pu, VOMdc=0.8*VDDQ, Nom | |
| RON48Pu, VOMdc=0.8*VDDQ, Max | |
| RON48Pu, VOHdc=0.95*VDDQ, Min | |
| RON48Pu, VOHdc=0.95*VDDQ, Nom | |
| RON48Pu, VOHdc=0.95*VDDQ, Max | |
| Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Min | |
| Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Max | |
| Mismatch DQ-DQ within byte variation pull-up, MMPudd, VOMdc=0.8*VDDQ, Max | |
| Mismatch DQ-DQ within byte variation pull-dn, MMPddd, VOMdc=0.8*VDDQ, Max | |
| Loopback RON34Pd, VOLdc=0.5*VDDQ, Min | |
| Loopback RON34Pd, VOLdc=0.5*VDDQ, Nom | |
| Loopback RON34Pd, VOLdc=0.5*VDDQ, Max | |
| Loopback RON34Pd, VOMdc=0.8*VDDQ, Min | |
| Loopback RON34Pd, VOMdc=0.8*VDDQ, Nom | |
| Loopback RON34Pd, VOMdc=0.8*VDDQ, Max | |
| Loopback RON34Pd, VOHdc=0.95*VDDQ, Min | |
| Loopback RON34Pd, VOHdc=0.95*VDDQ, Nom | |
| Loopback RON34Pd, VOHdc=0.95*VDDQ, Max | |
| Loopback RON34Pu, VOLdc=0.5*VDDQ, Min | |
| Loopback RON34Pu, VOLdc=0.5*VDDQ, Nom | |
| Loopback RON34Pu, VOLdc=0.5*VDDQ, Max | |
| Loopback RON34Pu, VOMdc=0.8*VDDQ, Min | |
| Loopback RON34Pu, VOMdc=0.8*VDDQ, Nom | |
| Loopback RON34Pu, VOMdc=0.8*VDDQ, Max | |
| Loopback RON34Pu, VOHdc=0.95*VDDQ, Min | |
| Loopback RON34Pu, VOHdc=0.95*VDDQ, Nom | |
| Loopback RON34Pu, VOHdc=0.95*VDDQ, Max | |
| Loopback Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Min | |
| Loopback Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Max | |
| Loopback Mismatch LBDQS-LBDQ within device variation pull-up, MMPudd, VOMdc=0.8*VDDQ, Max | |
| Loopback Mismatch LBDQS-LBDQ within device variation pull-dn, MMPddd, VOMdc=0.8*VDDQ, Max | |
| Loopback LBDQS Output Low Time, tLBQSL, MIN (DDR5-3200 to 4800) | |
| Loopback LBDQS Output High Time, tLBQSH, MIN (DDR5-3200 to 4800) | |
| Loopback LBDQS to LBDQ Skew, tLBDQSQ, MIN (DDR5-3200 to 4800) | |
| Loopback LBDQ Output Time from LBDQS, tLBQH, MIN (DDR5-3200 to 4800) | |
| Loopback Data valid window (tLBQH-tLBDQSQ) of each UI per DRAM, tLBDVW, MIN (DDR5-3200 to 4800) | |
| Alert_n output RONPd, VOLdc=0.1*VDDQ, Min | |
| Alert_n output RONPd, VOLdc=0.1*VDDQ, Max | |
| Alert_n output RONPd, VOMdc=0.8*VDDQ, Min | |
| Alert_n output RONPd, VOMdc=0.8*VDDQ, Max | |
| Alert_n output RONPd, VOHdc=0.95*VDDQ, Min | |
| Alert_n output RONPd, VOHdc=0.95*VDDQ, Max | |
| CT Mode RONPu_CT, VOBdc=0.2xVDDQ, Max | |
| CT Mode RONPu_CT, VOLdc=0.5xVDDQ, Max | |
| CT Mode RONPu_CT, VOMdc=0.8xVDDQ, Max | |
| CT Mode RONPu_CT, VOHdc=0.95xVDDQ, Max | |
| Single-ended Output high measurement level VOH (for output SR), DDR5-3200-6400 | |
| Single-ended Output low measurement level VOL (for output SR), DDR5-3200-6400 | |
| Single-ended Output high measurement level VOH for Loopback Signals (for output SR), DDR5-3200-6400 | |
| Single-ended Output low measurement level VOL for Loopback Signals (for output SR), DDR5-3200-6400 | |
| Single-ended output slew rate, SRQse, MIN (DDR5-3200 to 4800) | |
| Single-ended output slew rate, SRQse, MAX (DDR5-3200 to 4800) | |
| Differential Output high measurement level VOHdiff (for output SR), DDR5-3200-6400 | |
| Differential Output low measurement level VOLdiff (for output SR), DDR5-3200-6400 | |
| Differential output slew rate, SRQdiff, MIN (DDR5-3200 to 4800) | |
| Differential output slew rate, SRQdiff, MAX (DDR5-3200 to 4800) | |
| Tx DQS Rj RMS Value of 1-UI Jitter without BUJ, tTx_DQS_1UI_Rj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQS Dj pp Value of 1-UI Jitter without BUJ, tTx_DQS_1UI_Dj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQS Rj RMS Value of N-UI jitter without BUJ (1<N<4), tTx_DQS_NUI_Rj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4), tTx_DQS_NUI_Dj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQ Rj RMS of 1-UI jitter without BUJ, tTx_DQ_1UI_Rj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQ Dj pp 1-UI jitter without BUJ, tTx_DQ_1UI_Dj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQ Rj RMS of N-UI jitter without BUJ (1<N<4), tTx_DQ_NUI_Rj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQ Dj pp N-UI jitter without BUJ (1<N<4), tTx_DQ_NUI_Dj_NoBUJ, MAX (DDR5-3200 to 4800) | |
| Tx DQ Delay of any data lane relative to strobe lane, tTx_DQS2DQ, MIN (DDR5-3200 to 4800) | |
| Tx DQ Delay of any data lane relative to strobe lane, tTx_DQS2DQ, MAX (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Height, 1UI skew, TxEH_DQ_SES_1UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Width, 1UI skew, TxEW_DQ_SES_1UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Height, 2UI skew, TxEH_DQ_SES_2UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Width, 2UI skew, TxEW_DQ_SES_2UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Height, 3UI skew, TxEH_DQ_SES_3UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Width, 3UI skew, TxEW_DQ_SES_3UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Height, 4UI skew, TxEH_DQ_SES_4UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Width, 4UI skew, TxEW_DQ_SES_4UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Height, 5UI skew, TxEH_DQ_SES_5UI, MIN (DDR5-3200 to 4800) | |
| Tx DQ Stressed Eye Width, 5UI skew, TxEW_DQ_SES_5UI, MIN (DDR5-3200 to 4800) | |
| Module configuration | |
| Module Current note | |
| Module overall length (Front, outer) | |
| Module length (Front, inner) | |
| Module height (left edge) | |
| Height to notch / feature | |
| Contact/key dimension | |
| Top edge thickness/feature | |
| Edge feature dimension | |
| PCB / edge thickness | |
| Detail E dimension | |
| Detail F dimension | |
| Contact pitch | |
| Notch/key dimension | |
| Registering Clock Driver feature dimension | |
| Contact length (Detail of Contacts A, F) | |
| Contact dimension (Detail of Contacts A, F) | |
| Contact dimension (Detail of Contacts E) | |
| Contact dimension (Detail of Contacts B) | |
| Pin number callout (Detail of Contacts B) | |
| Contact dimension (Detail of Contacts C) | |
| Pin number callout (Detail of Contacts C) | |
| Contact dimension (Detail of Contacts D) | |
| Contact length (Detail of Contacts D) | |
| Non-metallized keep out area (Detail of Contacts A, F) | |
| Keep out area max dimension (Detail of Contacts A, F) | |
| Non-metallized keep out area (Detail of Contacts D) | |
| Keep out area max dimension (Detail of Contacts D) | |
| Component callout | |
| Section / Module configuration | |
| Module Current measurement note | |
| Overall length (outer) | |
| Length (inner) | |
| Width segment | |
| Height (overall) | |
| Height segment | |
| Thickness (PCB/contact) | |
| Edge dimension | |
| Notch/dimension | |
| Pin reference | |
| Component label | |
| Contacts A,F dimension | |
| Contacts E dimension | |
| Contacts B dimension | |
| Contacts B pin reference | |
| Contacts C dimension | |
| Contacts C pin reference | |
| Contacts D dimension | |
| Keep-out note | |
| Keep-out max | |
| Contacts dimension | |
| View label | |
| Disclaimer | |
| Intended use | |
| Bank configuration (x4/x8) | |
| Bank configuration (x16) | |
| Bank Group | |
| Burst length support | |
| Feature | |
| Training mode | |
| Absolute Maximum DC Rating - Voltage on VDD pin relative to Vss | |
| Absolute Maximum DC Rating - Voltage on VDDQ pin relative to Vss | |
| Absolute Maximum DC Rating - Voltage on VPP pin relative to Vss | |
| Absolute Maximum DC Rating - Voltage on any pin relative to Vss | |
| Absolute Maximum DC Rating - Storage Temperature | |
| tREFI1 REFab Normal, 0°C <= TCASE <= 85°C | |
| tREFI1 REFab Normal, 85°C < TCASE <= 95°C | |
| tREFI2 REFab Fine Granularity, 0°C <= TCASE <= 85°C | |
| tREFI2 REFab Fine Granularity, 85°C < TCASE <= 95°C | |
| tREFIsb REFsb Fine Granularity, 0°C <= TCASE <= 85°C | |
| tREFIsb REFsb Fine Granularity, 85°C < TCASE <= 95°C | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Min. | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Typ. | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Max. | |
| Recommended DC Operating Condition - VDD Z(f) Spec Freq: 2Mhz to 10Mhz Zmax | |
| Recommended DC Operating Condition - VDD Z(f) Spec Freq: 20Mhz Zmax | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Min. | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Typ. | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Max. | |
| Recommended DC Operating Condition - VDDQ Z(f) Spec Freq: 2Mhz to 10Mhz Zmax | |
| Recommended DC Operating Condition - VDDQ Z(f) Spec Freq: 20Mhz Zmax | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Min. | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Typ. | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Max. | |
| Recommended DC Operating Condition - VPP Z(f) Spec Freq: 2Mhz to 10Mhz Zmax | |
| Recommended DC Operating Condition - VPP Z(f) Spec Freq: 20Mhz Zmax | |
| Table title | |
| RON34Pd VOLdc=0.5*VDDQ | |
| RON34Pd VOMdc=0.8*VDDQ | |
| RON34Pd VOHdc=0.95*VDDQ | |
| RON34Pu VOLdc=0.5*VDDQ | |
| RON34Pu VOMdc=0.8*VDDQ | |
| RON34Pu VOHdc=0.95*VDDQ | |
| RON48Pd VOLdc=0.5*VDDQ | |
| RON48Pd VOMdc=0.8*VDDQ | |
| RON48Pd VOHdc=0.95*VDDQ | |
| RON48Pu VOLdc=0.5*VDDQ | |
| RON48Pu VOMdc=0.8*VDDQ | |
| RON48Pu VOHdc=0.95*VDDQ | |
| Mismatch between pull-up and pull-down, MMPuPd; VOMdc=0.8*VDDQ | |
| Mismatch DQ-DQ within byte variation pull-up, MMPudd; VOMdc=0.8*VDDQ | |
| Mismatch DQ-DQ within byte variation pull-dn, MMPddd; VOMdc=0.8*VDDQ | |
| NOTE 1 | |
| NOTE 2 | |
| NOTE 3 | |
| NOTE 4 | |
| NOTE 5 | |
| MMPuPd formula | |
| MMPudd formula | |
| MMPddd formula | |
| Revision | |
| Dimension units | |
| Tolerance note | |
| Front overall width (outer) | |
| Front overall width (inner) | |
| Front segment width | |
| Height dimension | |
| Front height dimension | |
| Front bottom dimension | |
| Back overall width | |
| Back vertical dimension | |
| Detail A registering clock driver dimension | |
| Detail A label | |
| Detail F components | |
| Side thickness | |
| Side note | |
| Detail dimension | |
| Detail of Contacts A,F dimension | |
| Detail of Contacts B dimension | |
| Detail of Contacts B pin reference | |
| Detail of Contacts C dimension | |
| Detail of Contacts C pin reference | |
| Detail of Contacts D dimension | |
| Detail of Contacts D keep-out note | |
| Detail of Contacts E dimension | |
| Detail of Contacts E keep-out note | |
| Revision date | |
| Page number | |
| Module Type (decoder, R) | |
| Shared device-level electrical/AC/DC specification set (pages 22-48) | |
| RON34Pd @ VOLdc=0.5*VDDQ, Min | |
| RON34Pd @ VOLdc=0.5*VDDQ, Nom | |
| RON34Pd @ VOLdc=0.5*VDDQ, Max | |
| RON34Pd @ VOMdc=0.8*VDDQ, Min | |
| RON34Pd @ VOMdc=0.8*VDDQ, Max | |
| RON34Pd @ VOHdc=0.95*VDDQ, Min | |
| RON34Pd @ VOHdc=0.95*VDDQ, Max | |
| RON34Pu @ VOLdc=0.5*VDDQ, Min | |
| RON34Pu @ VOLdc=0.5*VDDQ, Max | |
| RON48Pd @ VOLdc=0.5*VDDQ, Min | |
| RON48Pd @ VOLdc=0.5*VDDQ, Max | |
| RON48Pu @ VOLdc=0.5*VDDQ, Min | |
| RON48Pu @ VOLdc=0.5*VDDQ, Max | |
| Mismatch pull-up/pull-down MMPuPd @ VOMdc=0.8*VDDQ, Min | |
| Mismatch pull-up/pull-down MMPuPd @ VOMdc=0.8*VDDQ, Max | |
| Mismatch DQ-DQ within byte pull-up MMPudd, Max | |
| Mismatch DQ-DQ within byte pull-dn MMPddd, Max | |
| Loopback RON34Pd @ VOLdc=0.5*VDDQ, Min | |
| Loopback RON34Pd @ VOLdc=0.5*VDDQ, Max | |
| Loopback Mismatch MMPuPd, Min | |
| Loopback Mismatch MMPuPd, Max | |
| Loopback LBDQS Output Low Time tLBQSL, Min | |
| Loopback LBDQS Output High Time tLBQSH, Min | |
| Loopback LBDQS to LBDQ Skew tLBDQSQ, Min | |
| Loopback LBDQ Output Time from LBDQS tLBQH, Min | |
| Loopback Data valid window tLBDVW, Min | |
| Alert_n RONPd @ VOLdc=0.1*VDDQ, Min | |
| Alert_n RONPd @ VOLdc=0.1*VDDQ, Max | |
| Alert_n RONPd @ VOMdc=0.8*VDDQ, Min | |
| Alert_n RONPd @ VOHdc=0.95*VDDQ, Max | |
| CT mode RONPd_CT @ VOBdc=0.2*VDDQ, Max | |
| CT mode RONPd_CT @ VOLdc=0.5*VDDQ, Max | |
| CT mode RONPd_CT @ VOMdc=0.8*VDDQ, Max | |
| CT mode RONPd_CT @ VOHdc=0.95*VDDQ, Max | |
| CT mode uncalibrated drive strength tolerance | |
| VOH output high measurement level (for output SR) | |
| VOL output low measurement level (for output SR) | |
| Single ended output slew rate SRQse, Min | |
| Single ended output slew rate SRQse, Max | |
| VOHdiff differential output high measurement level | |
| VOLdiff differential output low measurement level | |
| Differential output slew rate SRQdiff, Min | |
| Differential output slew rate SRQdiff, Max | |
| Tx DQS Rj RMS 1-UI jitter without BUJ, Max | |
| Tx DQS Dj pp 1-UI jitter without BUJ, Max | |
| Tx DQS Dj pp N-UI jitter without BUJ (1<N<4), Max | |
| Tx DQS Rj max value note | |
| Tx DQ Dj pp 1-UI jitter without BUJ, Max | |
| Tx DQ Dj pp N-UI jitter without BUJ (1<N<4), Max | |
| Tx DQS2DQ delay of any data lane relative to strobe lane, Min | |
| Tx DQS2DQ delay of any data lane relative to strobe lane, Max | |
| TxEW_DQ_SES_1UI Eye Width at 1UI skew, Min | |
| TxEW_DQ_SES_2UI Eye Width at 2UI skew, Min | |
| TxEW_DQ_SES_3UI Eye Width at 3UI skew, Min | |
| TxEH_DQ_SES Eye Height at transmitter | |
| Tx DQ Stressed Eye BER / confidence level | |
| DDR5-4400B CL-nRCD-nRP | |
| DDR5-4400B tAA internal read command to first data | |
| DDR5-4400B tRCD ACT to internal read or write delay | |
| DDR5-4400B tRP row precharge time | |
| DDR5-4400B tRAS ACT to PRE command period, min | |
| DDR5-4400B tRC ACT to ACT or REF command period | |
| DDR5-4400B CWL CAS write latency | |
| DDR5-4400 Supported CL | |
| DDR5-4400B tCK(AVG) min @ CL=36 CWL=34 | |
| DDR5-4800B CL-nRCD-nRP | |
| DDR5-4800B tAA internal read command to first data | |
| DDR5-4800B tRCD ACT to internal read or write delay | |
| DDR5-4800B tRP row precharge time | |
| DDR5-4800B tRC ACT to ACT or REF command period | |
| DDR5-4800B CWL CAS write latency | |
| DDR5-4800B tCK(AVG) min @ CL=40 CWL=38 | |
| DDR5-4800 Supported CL | |
| Specification type | |
| Note | |
| Die basis | |
| Document date | |
| Description | |
| Bank Groups | |
| Training Mode | |
| Pin 1 | |
| VIN_BULK | |
| VIN_MGMT | |
| DQ0_A - DQ31_A | |
| Drawing title | |
| Register input signal | |
| Register output routing (A side) | |
| Register output routing (B side) | |
| DRAM device placement (front row) | |
| DRAM device placement (back row) | |
| Note 1 (resistor value) | |
| DRAM device net (A side, top row) | |
| Address net to DRAM (A side, top) | |
| DRAM data net group (A side, top) | |
| DRAM data byte net group (A side, top) | |
| Address net to DRAM (B side, bottom) | |
| DRAM device net (B side, bottom row) | |
| DRAM data byte net group (B side, bottom) | |
| Note 2 (DRAM ZQ resistor) | |
| VDD - Voltage on VDD pin relative to Vss | |
| VDDQ - Voltage on VDDQ pin relative to Vss | |
| VPP - Voltage on VPP pin relative to Vss | |
| VIN, VOUT - Voltage on any pin relative to Vss | |
| TSTG - Storage Temperature | |
| tREFI1 REFab Normal (0C<=TCASE<=85C) | |
| tREFI1 REFab Normal (85C<TCASE<=95C) | |
| tREFI2 REFab Fine Granularity (0C<=TCASE<=85C) | |
| tREFI2 REFab Fine Granularity (85C<TCASE<=95C) | |
| tREFIsb REFsb Fine Granularity (0C<=TCASE<=85C) | |
| tREFIsb REFsb Fine Granularity (85C<TCASE<=95C) | |
| VDD Device Supply Voltage - Min | |
| VDD Device Supply Voltage - Typ | |
| VDD Device Supply Voltage - Max | |
| VDD Z(f) Spec 2MHz to 10MHz Zmax | |
| VDD Z(f) Spec 20MHz Zmax | |
| VDDQ Supply Voltage for I/O - Min | |
| VDDQ Supply Voltage for I/O - Typ | |
| VDDQ Supply Voltage for I/O - Max | |
| VDDQ Z(f) Spec 2MHz to 10MHz Zmax | |
| VDDQ Z(f) Spec 20MHz Zmax | |
| VPP Core Power Voltage - Min | |
| VPP Core Power Voltage - Typ | |
| VPP Core Power Voltage - Max | |
| VPP Z(f) Spec 2MHz to 10MHz Zmax | |
| VPP Z(f) Spec 20MHz Zmax | |
| Rx Mask voltage - p-p (VciVW) - Max | |
| Rx Timing Window (TcIVW) - Max | |
| CA Input Pulse Amplitude (VIHL_AC) | |
| CA Input Pulse Width (TcIPW) | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - Max | |
| DRAM Reference clock frequency (tCK) - Min | |
| DRAM Reference clock frequency (tCK) - Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) - Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - Max | |
| Rj RMS value of N-UI Jitter N=2,3 (tCK_NUI_Rj_NoBUJ) - Max | |
| Dj pp value of N-UI Jitter N=2,3 (tCK_NUI_Dj_NoBUJ) - Max | |
| Tj value of N-UI Jitter N=2,3 (tCK_NUI_Tj_NoBUJ) - Max | |
| Rj RMS value of N-UI Jitter N=4..30 (tCK_NUI_Rj_NoBUJ) - Max | |
| Dj pp value of N-UI Jitter N=4..30 (tCK_NUI_Dj_NoBUJ) - Max | |
| Tj value of N-UI Jitter N=4..30 (tCK_NUI_Tj_NoBUJ) - Max | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - Max (DDR5-3200-4800) | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - Max (DDR5-6800-8400) | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - Max | |
| VIHdiffCK Differential input high measurement level (CK_t, CK_c) | |
| VILdiffCK Differential input low measurement level (CK_t, CK_c) | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - Max | |
| DQ Timing Width (tRx_DQ_tMargin) - Min | |
| Degradation of timing width with DCD injection in DQS (tRx_DQ_tMargin_DQS_DCD) - Max | |
| Degradation of timing width with Rj injection in DQS (tRx_DQ_tMargin_DQS_Rj) - Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (tRx_DQ_tMargin_DQS_DCD_Rj) - Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) - Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) - Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - Max | |
| DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) - Max (DDR5-3200-4800) | |
| VIHdiffDQS Differential input high measurement level (DQS_t, DQS_c) | |
| VILdiffDQS Differential input low measurement level (DQS_t, DQS_c) | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - Max | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - Max | |
| Eye height of stressed eye Golden Ref Channel 1 (RxEH) - Max | |
| Eye width of stressed eye Golden Ref Channel 1 (RxEW) - Max | |
| Vswing stress to meet above data eye (Vswing) - Max | |
| Injected sinusoidal jitter at 200 MHz (Sj) - Min | |
| Injected sinusoidal jitter at 200 MHz (Sj) - Max | |
| Injected Random wide band (10MHz-1GHz) Jitter (Rj) - Min | |
| Injected Random wide band (10MHz-1GHz) Jitter (Rj) - Max | |
| Injected voltage noise PRBS23 or 2.1 GHz (Vnoise) - Min | |
| Injected voltage noise PRBS23 or 2.1 GHz (Vnoise) - Max | |
| Golden Reference Channel 1 Characteristics | |
| tCT_IS - Min | |
| tCT_Enable - Min | |
| tCT_Valid - Max | |
| TEN AC Input High Voltage (VIH(AC)_TEN) - Min | |
| TEN AC Input High Voltage (VIH(AC)_TEN) - Max | |
| TEN DC Input High Voltage (VIH(DC)_TEN) - Min | |
| TEN DC Input High Voltage (VIH(DC)_TEN) - Max | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) - Min | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) - Max | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) - Min | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) - Max | |
| TEN Input signal Falling time (TF_input_TEN) - Max | |
| TEN Input signal Rising time (TR_input_TEN) - Max | |
| AC Input High Voltage (VIH(AC)_RESET) - Min | |
| AC Input High Voltage (VIH(AC)_RESET) - Max | |
| DC Input High Voltage (VIH(DC)_RESET) - Min | |
| DC Input High Voltage (VIH(DC)_RESET) - Max | |
| DC Input Low Voltage (VIL(DC)_RESET) - Min | |
| DC Input Low Voltage (VIL(DC)_RESET) - Max | |
| AC Input Low Voltage (VIL(AC)_RESET) - Min | |
| AC Input Low Voltage (VIL(AC)_RESET) - Max | |
| Rising time (TR_RESET) - Max | |
| RESET pulse width (tPW_RESET) - Min | |
| RON34Pd VOLdc=0.5*VDDQ Min | |
| RON34Pd VOLdc=0.5*VDDQ Nom | |
| RON34Pd VOLdc=0.5*VDDQ Max | |
| RON34Pd VOMdc=0.8*VDDQ Min | |
| RON34Pd VOMdc=0.8*VDDQ Max | |
| RON34Pd VOHdc=0.95*VDDQ Min | |
| RON34Pd VOHdc=0.95*VDDQ Max | |
| RON34Pu VOLdc=0.5*VDDQ Min | |
| RON34Pu VOLdc=0.5*VDDQ Max | |
| RON34Pu VOMdc=0.8*VDDQ Min | |
| RON34Pu VOMdc=0.8*VDDQ Max | |
| RON34Pu VOHdc=0.95*VDDQ Min | |
| RON34Pu VOHdc=0.95*VDDQ Max | |
| RON48Pd VOLdc=0.5*VDDQ Min | |
| RON48Pd VOLdc=0.5*VDDQ Max | |
| RON48Pd VOMdc=0.8*VDDQ Min | |
| RON48Pd VOMdc=0.8*VDDQ Max | |
| RON48Pd VOHdc=0.95*VDDQ Min | |
| RON48Pd VOHdc=0.95*VDDQ Max | |
| RON48Pu VOLdc=0.5*VDDQ Min | |
| RON48Pu VOLdc=0.5*VDDQ Max | |
| RON48Pu VOMdc=0.8*VDDQ Min | |
| RON48Pu VOMdc=0.8*VDDQ Max | |
| RON48Pu VOHdc=0.95*VDDQ Min | |
| RON48Pu VOHdc=0.95*VDDQ Max | |
| Mismatch pull-up/pull-down MMPuPd Min | |
| Mismatch pull-up/pull-down MMPuPd Max | |
| Mismatch DQ-DQ within byte pull-up MMPudd Max | |
| Mismatch DQ-DQ within byte pull-dn MMPddd Max | |
| LB RON34Pd VOLdc=0.5*VDDQ Min | |
| LB RON34Pd VOLdc=0.5*VDDQ Max | |
| LB RON34Pd VOMdc=0.8*VDDQ Min | |
| LB RON34Pd VOMdc=0.8*VDDQ Max | |
| LB RON34Pd VOHdc=0.95*VDDQ Min | |
| LB RON34Pd VOHdc=0.95*VDDQ Max | |
| LB RON34Pu VOLdc=0.5*VDDQ Min | |
| LB RON34Pu VOLdc=0.5*VDDQ Max | |
| LB RON34Pu VOMdc=0.8*VDDQ Min | |
| LB RON34Pu VOMdc=0.8*VDDQ Max | |
| LB RON34Pu VOHdc=0.95*VDDQ Min | |
| LB RON34Pu VOHdc=0.95*VDDQ Max | |
| LB Mismatch MMPuPd Min | |
| LB Mismatch MMPuPd Max | |
| LB Mismatch LBDQS-LBDQ pull-up MMPudd Max | |
| LB Mismatch LBDQS-LBDQ pull-dn MMPddd Max | |
| tLBQSL Loopback LBDQS Output Low Time Min | |
| tLBQSH Loopback LBDQS Output High Time Min | |
| tLBDQSQ Loopback LBDQS to LBDQ Skew Min | |
| tLBQH Loopback LBDQ Output Time from LBDQS Min | |
| tLBDVW Loopback Data valid window Min | |
| Alert_n RONPd VOLdc=0.1*VDDQ Min | |
| Alert_n RONPd VOLdc=0.1*VDDQ Max | |
| Alert_n RONPd VOMdc=0.8*VDDQ Min | |
| Alert_n RONPd VOMdc=0.8*VDDQ Max | |
| Alert_n RONPd VOHdc=0.95*VDDQ Min | |
| Alert_n RONPd VOHdc=0.95*VDDQ Max | |
| CT RONPd_CT VOBdc=0.2*VDDQ Max | |
| CT RONPd_CT VOLdc=0.5*VDDQ Max | |
| CT RONPd_CT VOMdc=0.8*VDDQ Max | |
| CT RONPd_CT VOHdc=0.95*VDDQ Max | |
| CT RONPu_CT VOBdc=0.2*VDDQ Max | |
| CT RONPu_CT VOLdc=0.5*VDDQ Max | |
| CT RONPu_CT VOMdc=0.8*VDDQ Max | |
| CT RONPu_CT VOHdc=0.95*VDDQ Max | |
| VOH Output high measurement level (for output SR) | |
| VOL Output low measurement level (for output SR) | |
| LB VOH Output high measurement level (for output SR) | |
| LB VOL Output low measurement level (for output SR) | |
| SRQse Single ended output slew rate Min | |
| SRQse Single ended output slew rate Max | |
| VOHdiff Differential output high measurement level (for output SR) | |
| VOLdiff Differential output low measurement level (for output SR) | |
| SRQdiff Differential output slew rate Min | |
| SRQdiff Differential output slew rate Max | |
| tTx_DQS_1UI_Rj_NoBUJ Rj RMS 1-UI without BUJ Max | |
| tTx_DQS_1UI_Dj_NoBUJ Dj pp 1-UI without BUJ Max | |
| tTx_DQS_NUI_Rj_NoBUJ Rj RMS N-UI without BUJ (1<N<4) Max | |
| tTx_DQS_NUI_Dj_NoBUJ Dj pp N-UI without BUJ (1<N<4) Max | |
| tTx_DQ_1UI_Rj_NoBUJ Rj RMS 1-UI without BUJ Max | |
| tTx_DQ_1UI_Dj_NoBUJ Dj pp 1-UI without BUJ Max | |
| tTx_DQ_NUI_Rj_NoBUJ Rj RMS N-UI without BUJ (1<N<4) Max | |
| tTx_DQ_NUI_Dj_NoBUJ Dj pp N-UI without BUJ (1<N<4) Max | |
| tTx_DQS2DQ Delay of any data lane relative to strobe lane Min | |
| tTx_DQS2DQ Delay of any data lane relative to strobe lane Max | |
| Tx DQ Rj max value note | |
| TxEH_DQ_SES_1UI Eye Height skew 1UI Min | |
| TxEW_DQ_SES_1UI Eye Width skew 1UI Min | |
| TxEH_DQ_SES_2UI Eye Height skew 2UI Min | |
| TxEW_DQ_SES_2UI Eye Width skew 2UI Min | |
| TxEH_DQ_SES_3UI Eye Height skew 3UI Min | |
| TxEW_DQ_SES_3UI Eye Width skew 3UI Min | |
| TxEH_DQ_SES_4UI Eye Height skew 4UI Min | |
| TxEW_DQ_SES_4UI Eye Width skew 4UI Min | |
| TxEH_DQ_SES_5UI Eye Height skew 5UI Min | |
| TxEW_DQ_SES_5UI Eye Width skew 5UI Min | |
| TCASE for IDD/IDDQ/IPP measurement | |
| MID-LEVEL definition (VREF) | |
| Burst Length for IDD patterns | |
| IDD6N Self Refresh Normal Temp Range TCASE | |
| IDD6E Self Refresh Extended Temp Range TCASE | |
| Internal read command to first data (tAA) min | |
| ACT to internal read or write delay time (tRCD) min | |
| Row Precharge Time (tRP) min | |
| ACT to ACT or REF command period (tRC) min | |
| CAS Write Latency (CWL) | |
| 3200C tAAmin | |
| 3200C Read CL / Write CWL | |
| 3200C tCK(AVG) min | |
| 3200C tCK(AVG) max | |
| 3200BN/3200B tAAmin | |
| 3200BN/3200B tRPmin | |
| 3200BN/3200B Read CL / Write CWL | |
| 3200BN/3200B tCK(AVG) min | |
| 3200BN/3200B tCK(AVG) max | |
| 3200AN tAAmin | |
| 3200AN tRPmin | |
| 3200AN Read CL / Write CWL | |
| 3200AN tCK(AVG) | |
| 3200AN (15.000) tAA/tRP | |
| 3600C tAAmin | |
| 3600C tRPmin | |
| 3600C Read CL / Write CWL | |
| 3600C tCK(AVG) min | |
| 3600C tCK(AVG) max | |
| 3600BN/3600B tAAmin | |
| 3600BN/3600B tRPmin | |
| 3600BN/3600B Read CL / Write CWL | |
| 3600BN/3600B tCK(AVG) min | |
| 3600BN/3600B tCK(AVG) max | |
| 3600AN tAA/tRP | |
| 3600AN Read CL / Write CWL | |
| 3600AN tCK(AVG) | |
| 4000C tAAmin | |
| 4000C tRPmin | |
| 4000C Read CL / Write CWL | |
| 4000C tCK(AVG) min | |
| 4000C tCK(AVG) max | |
| 4000BN/4000B tAAmin | |
| 4000BN/4000B tRPmin | |
| 4000BN/4000B Read CL / Write CWL | |
| 4000BN/4000B tCK(AVG) min | |
| 4000BN/4000B tCK(AVG) max | |
| 4000AN tAA/tRP | |
| 4000AN Read CL / Write CWL | |
| 4000AN tCK(AVG) | |
| 4400C tAAmin | |
| 4400C tRPmin | |
| 4400C Read CL / Write CWL | |
| 4400C tCK(AVG) min | |
| 4400C tCK(AVG) max | |
| 4400BN/4400B tAA/tRP | |
| 4400BN/4400B Read CL / Write CWL | |
| 4400BN/4400B tCK(AVG) min | |
| 4400BN/4400B tCK(AVG) max | |
| 4400AN tAA/tRP | |
| 4400AN Read CL / Write CWL | |
| 4400AN tCK(AVG) | |
| Supported CL | |
| 3200BN/3200B tAA/tRP | |
| 3200AN tAA/tRP | |
| 3600C tAA/tRP | |
| 3600BN/3600B tAA/tRP | |
| 4000BN/4000B tAA/tRP | |
| 4800C tAA/tRP | |
| 4800C Read CL / Write CWL | |
| 4800C tCK(AVG) min | |
| 4800C tCK(AVG) max | |
| 4800BN tAA/tRP | |
| 4800BN Read CL / Write CWL | |
| 4800BN tCK(AVG) min | |
| 4800BN tCK(AVG) max | |
| 4800B tAAmin | |
| 4800B tRPmin | |
| 4800B Read CL / Write CWL | |
| 4800B tCK(AVG) min | |
| 4800B tCK(AVG) max | |
| 4800AN tAA/tRP | |
| 4800AN Read CL / Write CWL | |
| 4800AN tCK(AVG) | |
| Dimensional tolerance (unless otherwise stated) | |
| Module overall length (outer) | |
| Module length (inner) | |
| Height to feature | |
| Top edge dimension | |
| Detail A dimension | |
| Edge dimension (top right) | |
| Segment length (left) | |
| Segment length (right) | |
| Vertical dimension (right side) | |
| Back view vertical dimension | |
| Side view dimension | |
| Registering Clock Driver dimension | |
| Contact thickness (Detail A,F) | |
| Contact dimension (Detail A,F) | |
| Contact length (Detail A,F) | |
| Contact dimension (Detail E) | |
| Contact dimension (Detail B) | |
| Pin reference (Detail B) | |
| Contact dimension (Detail C) | |
| Pin reference (Detail C) | |
| Contact thickness (Detail D) | |
| Contact dimension (Detail D) | |
| Non-metalized keep out area note (Detail A,F) | |
| Keep out area dimension (Detail A,F) | |
| Non-metalized keep out area note (Detail D) | |
| Keep out area dimension (Detail D) | |
| Component callout (Detail F) | |
| Detail callouts present | |
| Based on | |
| Manufacturer | |
| Voltage on VDD pin relative to Vss (Absolute Maximum) | |
| Voltage on VDDQ pin relative to Vss (Absolute Maximum) | |
| Voltage on VPP pin relative to Vss (Absolute Maximum) | |
| Voltage on any pin relative to Vss (Absolute Maximum) | |
| Storage Temperature (Absolute Maximum) | |
| tREFI1 (REFab Normal), 0°C<=TCASE<=85°C | |
| tREFI1 (REFab Normal), 85°C<TCASE<=95°C | |
| tREFI2 (REFab Fine Granularity), 0°C<=TCASE<=85°C | |
| tREFI2 (REFab Fine Granularity), 85°C<TCASE<=95°C | |
| tREFIsb (REFsb Fine Granularity), 0°C<=TCASE<=85°C | |
| tREFIsb (REFsb Fine Granularity), 85°C<TCASE<=95°C | |
| Device Supply Voltage VDD (Recommended DC, Typ) | |
| Device Supply Voltage VDD (Recommended DC, Min) | |
| Device Supply Voltage VDD (Recommended DC, Max) | |
| Supply Voltage for I/O VDDQ (Recommended DC, Typ) | |
| Supply Voltage for I/O VDDQ (Recommended DC, Min) | |
| Supply Voltage for I/O VDDQ (Recommended DC, Max) | |
| Core Power Voltage VPP (Recommended DC, Typ) | |
| Core Power Voltage VPP (Recommended DC, Min) | |
| Core Power Voltage VPP (Recommended DC, Max) | |
| Z(f) Spec Zmax (DC to 2MHz / 2MHz to 10MHz) for VDD/VDDQ/VPP | |
| Z(f) Spec Zmax (Freq: 20MHz) for VDD/VDDQ/VPP | |
| Rx Mask voltage - p-p (VciVW) Max | |
| Rx Timing Window (TcIVW) Max | |
| Input Slew Rate over VcIVW (SRIN_cIVW) Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) Max | |
| DRAM Reference clock frequency (tCK) Min | |
| DRAM Reference clock frequency (tCK) Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) Max | |
| Rj RMS value of N-UI Jitter, N=2,3 (tCK_NUI_Rj_NoBUJ) Max | |
| Dj pp value of N-UI Jitter, N=2,3 (tCK_NUI_Dj_NoBUJ) Max | |
| Tj value of N-UI Jitter, N=2,3 (tCK_NUI_Tj_NoBUJ) Max | |
| Rj RMS value of N-UI Jitter, N=4..30 (tCK_NUI_Rj_NoBUJ) | |
| Dj pp value of N-UI Jitter, N=4..30 (tCK_NUI_Dj_NoBUJ) | |
| Tj value of N-UI Jitter, N=4..30 (tCK_NUI_Tj_NoBUJ) | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Max | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) Max | |
| Differential input high measurement level CK (VIHdiffCK) | |
| Differential input low measurement level CK (VILdiffCK) | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Max | |
| DQ Timing Width (tRx_DQ_tMargin) Min | |
| Degradation of timing width with DCD injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD) Max | |
| Degradation of timing width with Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_Rj) Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) Max | |
| DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) Max | |
| Differential input high measurement level DQS (VIHdiffDQS) | |
| Differential input low measurement level DQS (VILdiffDQS) | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max | |
| Eye height of stressed eye for Golden Reference Channel 1 Max | |
| Eye width of stressed eye Golden Reference Channel 1 Max | |
| Vswing stress to meet above data eye Max | |
| Injected sinusoidal jitter at 200 MHz (Sj) Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter (Rj) Max | |
| Injected voltage noise (PRBS23 / 2.1 GHz) (Vnoise) Max | |
| CT Mode AC parameter tCT_IS Min | |
| CT Mode AC parameter tCT_Enable Min | |
| CT Mode AC parameter tCT_Valid Max | |
| TEN AC Input High Voltage (VIH(AC)_TEN) Min | |
| TEN DC Input High Voltage (VIH(DC)_TEN) Min | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) Max | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) Max | |
| TEN Input signal Falling time (TF_input_TEN) Max | |
| TEN Input signal Rising time (TR_input_TEN) Max | |
| RESET_n AC Input High Voltage (VIH(AC)_RESET) Min | |
| RESET_n DC Input High Voltage (VIH(DC)_RESET) Min | |
| RESET_n DC Input Low Voltage (VIL(DC)_RESET) Max | |
| RESET_n AC Input Low Voltage (VIL(AC)_RESET) Max | |
| RESET_n Rising time (TR_RESET) Max | |
| RESET pulse width (tPW_RESET) Min | |
| RON34Pd VOLdc=0.5*VDDQ (Output Driver DC) Min/Nom/Max | |
| RON34Pd VOMdc=0.8*VDDQ Min/Nom/Max | |
| RON34Pd VOHdc=0.95*VDDQ Min/Nom/Max | |
| RON34Pu VOLdc=0.5*VDDQ Min/Nom/Max | |
| RON34Pu VOMdc=0.8*VDDQ Min/Nom/Max | |
| RON34Pu VOHdc=0.95*VDDQ Min/Nom/Max | |
| RON48Pd VOLdc=0.5*VDDQ Min/Nom/Max | |
| RON48Pd VOMdc=0.8*VDDQ Min/Nom/Max | |
| RON48Pd VOHdc=0.95*VDDQ Min/Nom/Max | |
| RON48Pu VOLdc=0.5*VDDQ Min/Nom/Max | |
| RON48Pu VOMdc=0.8*VDDQ Min/Nom/Max | |
| RON48Pu VOHdc=0.95*VDDQ Min/Nom/Max | |
| Mismatch between pull-up and pull-down (MMPuPd) VOMdc=0.8*VDDQ Min/Max | |
| Mismatch DQ-DQ within byte variation pull-up (MMPudd) Max | |
| Mismatch DQ-DQ within byte variation pull-dn (MMPddd) Max | |
| Loopback RON34Pd VOLdc=0.5*VDDQ Min/Nom/Max | |
| Loopback RON34Pd VOMdc=0.8*VDDQ Min/Nom/Max | |
| Loopback RON34Pd VOHdc=0.95*VDDQ Min/Nom/Max | |
| Loopback RON34Pu VOLdc=0.5*VDDQ Min/Nom/Max | |
| Loopback RON34Pu VOMdc=0.8*VDDQ Min/Nom/Max | |
| Loopback RON34Pu VOHdc=0.95*VDDQ Min/Nom/Max | |
| Loopback Mismatch pull-up/pull-down (MMPuPd) Min/Max | |
| Loopback Mismatch LBDQS-LBDQ within device pull-up (MMPudd) Max | |
| Loopback Mismatch LBDQS-LBDQ within device pull-dn (MMPddd) Max | |
| Loopback LBDQS Output Low Time (tLBQSL) Min | |
| Loopback LBDQS Output High Time (tLBQSH) Min | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) Min | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) Min | |
| Loopback Data valid window (tLBDVW) Min | |
| Alert_n RONPd VOLdc=0.1*VDDQ Min/Max | |
| Alert_n RONPd VOMdc=0.8*VDDQ Min/Max | |
| Alert_n RONPd VOHdc=0.95*VDDQ Min/Max | |
| CT Mode RONPd_CT VOBdc=0.2*VDDQ Max | |
| CT Mode RONPd_CT VOLdc=0.5*VDDQ Max | |
| CT Mode RONPd_CT VOMdc=0.8*VDDQ Max | |
| CT Mode RONPd_CT VOHdc=0.95*VDDQ Max | |
| CT Mode RONPu_CT VOBdc=0.2*VDDQ Max | |
| CT Mode RONPu_CT VOLdc=0.5*VDDQ Max | |
| CT Mode RONPu_CT VOMdc=0.8*VDDQ Max | |
| CT Mode RONPu_CT VOHdc=0.95*VDDQ Max | |
| Single-ended Output high measurement level (VOH) | |
| Single-ended Output low measurement level (VOL) | |
| Single-ended Output high measurement level for Loopback (VOH) | |
| Single-ended Output low measurement level for Loopback (VOL) | |
| Single ended output slew rate (SRQse) Min | |
| Single ended output slew rate (SRQse) Max | |
| Differential output high measurement level (VOHdiff) | |
| Differential output low measurement level (VOLdiff) | |
| Differential output slew rate (SRQdiff) Min | |
| Differential output slew rate (SRQdiff) Max | |
| Tx DQS Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) Max | |
| Tx DQS Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) Max | |
| Tx DQS Rj RMS Value of N-UI jitter without BUJ (1<N<4) (tTx_DQS_NUI_Rj_NoBUJ) Max | |
| Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) (tTx_DQS_NUI_Dj_NoBUJ) Max | |
| Tx DQ Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) Max | |
| Tx DQ Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) Max | |
| Tx DQ Rj RMS of N-UI jitter without BUJ (1<N<4) (tTx_DQ_NUI_Rj_NoBUJ) Max | |
| Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) (tTx_DQ_NUI_Dj_NoBUJ) Max | |
| Tx DQ Delay of any data lane relative to strobe lane (tTx_DQS2DQ) Min | |
| Tx DQ Delay of any data lane relative to strobe lane (tTx_DQS2DQ) Max | |
| Tx DQ Eye Width at transmitter, skew DQ-DQS 1UI (TxEW_DQ_SES_1UI) Min | |
| Tx DQ Eye Height at transmitter, skew DQ-DQS 1UI (TxEH_DQ_SES_1UI) Min | |
| Tx DQ Eye Width at transmitter, skew DQ-DQS 2UI (TxEW_DQ_SES_2UI) Min | |
| Tx DQ Eye Width at transmitter, skew DQ-DQS 3UI (TxEW_DQ_SES_3UI) Min | |
| Tx DQ Eye Height at transmitter, skew DQ-DQS 2UI/3UI/4UI/5UI (TxEH_DQ_SES) Min | |
| Tx DQ Eye Width at transmitter, skew DQ-DQS 4UI/5UI (TxEW_DQ_SES) Min | |
| IDD0 - Operating One Bank Active-Precharge Current (symbol/definition) | |
| IDD0F - Operating Four Bank Active-Precharge Current (symbol/definition) | |
| IDD2N - Precharge Standby Current (symbol/definition) | |
| IDD2NT - Precharge Standby Non-Target Command Current (symbol/definition) | |
| IDD2P - Precharge Power-Down (symbol/definition) | |
| IDD3N - Active Standby Current (symbol/definition) | |
| IDD3P - Active Power-Down Current (symbol/definition) | |
| IDD4R - Operating Burst Read Current (symbol/definition) | |
| IDD4W - Operating Burst Write Current (symbol/definition) | |
| IDD5B - Burst Refresh Current Normal Refresh Mode (symbol/definition) | |
| IDD5F - Burst Refresh Current Fine Granularity Refresh Mode (symbol/definition) | |
| IDD5C - Burst Refresh Current Same Bank Refresh Mode (symbol/definition) | |
| IDD6N - Self Refresh Current Normal Temperature Range (symbol/definition) | |
| IDD6E - Self Refresh Current Extended Temperature Range (symbol/definition) | |
| IDD7 - Operating Bank Interleave Read Current (symbol/definition) | |
| IDD8 - Maximum Power Saving Deep Power Down Current (symbol/definition) | |
| IDD9 - MBIST Current (Optional) (symbol/definition) | |
| Note 1 - tolerance | |
| Front overall length (outer) | |
| Front overall length (inner) | |
| Front dimension (left) | |
| Front dimension (right) | |
| Front dimension | |
| Front module height | |
| Registering Clock Driver callout | |
| Back dimension | |
| Detail A radius | |
| Detail A pin callout | |
| Detail of Contacts A, F dimension | |
| Detail of Contacts B pin callout | |
| Detail of Contacts C pin callout | |
| Detail of Contacts D keep-out dimension | |
| Detail B keep-out note | |
| Keep-out dimension | |
| tREFI1 (REFab, Normal, 0C<=TCASE<=85C) | |
| tREFI1 (REFab, Normal, 85C<TCASE<=95C) | |
| tREFI2 (REFab, Fine Granularity, 0C<=TCASE<=85C) | |
| tREFI2 (REFab, Fine Granularity, 85C<TCASE<=95C) | |
| tREFIsb (REFsb, Fine Granularity, 0C<=TCASE<=85C) | |
| tREFIsb (REFsb, Fine Granularity, 85C<TCASE<=95C) | |
| VDD - Device Supply Voltage, Min | |
| VDD - Device Supply Voltage, Typ | |
| VDD - Device Supply Voltage, Max | |
| VDD - Z(f) DC to 2MHz Zmax | |
| VDD - Z(f) 20MHz Zmax | |
| VDDQ - Supply Voltage for I/O, Min | |
| VDDQ - Supply Voltage for I/O, Typ | |
| VDDQ - Supply Voltage for I/O, Max | |
| VDDQ - Z(f) DC to 2MHz Zmax | |
| VDDQ - Z(f) 20MHz Zmax | |
| VPP - Core Power Voltage, Min | |
| VPP - Core Power Voltage, Typ | |
| VPP - Core Power Voltage, Max | |
| VPP - Z(f) DC to 2MHz Zmax | |
| VPP - Z(f) 20MHz Zmax | |
| VciVW - Rx Mask voltage p-p, Max | |
| TcIVW - Rx Timing Window, Max | |
| VIHL_AC - CA Input Pulse Amplitude | |
| TcIPW - CA Input Pulse Width | |
| SRIN_cIVW - Input Slew Rate over VcIVW, Min | |
| SRIN_cIVW - Input Slew Rate over VcIVW, Max | |
| tCK_Duty_UI_Error - Duty Cycle Error, Max | |
| tCK_1UI_Rj_NoBUJ - Rj RMS 1-UI Jitter, Max | |
| tCK_1UI_Dj_NoBUJ - Dj pp 1-UI Jitter, Max | |
| tCK_1UI_Tj_NoBUJ - Tj 1-UI Jitter, Max | |
| tCK_NUI_Rj_NoBUJ (N=2,3) - Rj RMS, Max | |
| tCK_NUI_Dj_NoBUJ (N=2,3) - Dj pp, Max | |
| tCK_NUI_Tj_NoBUJ (N=2,3) - Tj, Max | |
| tCK_NUI_Rj_NoBUJ (N=4..30) - Rj RMS, Max | |
| tCK_NUI_Dj_NoBUJ (N=4..30) - Dj pp, Max | |
| tCK_NUI_Tj_NoBUJ (N=4..30) - Tj, Max | |
| VIX_CK_Ratio - Clock differential input crosspoint voltage ratio, Max | |
| VRx_CK - Input Clock Voltage Sensitivity (differential pp), Max | |
| VIHdiffCK - Differential input high measurement level (CK_t, CK_c) | |
| VILdiffCK - Differential input low measurement level (CK_t, CK_c) | |
| SRIdiff_CK - Differential Input Slew Rate for CK_t, CK_c, Min | |
| SRIdiff_CK - Differential Input Slew Rate for CK_t, CK_c, Max | |
| tRx_DQ_tMargin - DQ Timing Width, Min | |
| dtRx_DQ_tMargin_DQS_DCD - Degradation w/ DCD injection, Max | |
| dtRx_DQ_tMargin_DQS_Rj - Degradation w/ Rj injection, Max | |
| dtRx_DQ_tMargin_DQS_DCD_Rj - Degradation w/ DCD and Rj, Max | |
| tRx_DQS2DQ - Delay of data lane relative to DQS crossing, Min | |
| tRx_DQS2DQ - Delay of data lane relative to DQS crossing, Max | |
| tRx_DQS2DQ - Delay, Max | |
| tRx_DQS_DCD - Applied DCD to the DQS, Max | |
| tRx_DQS_Rj - Applied Rj RMS to the DQS, Max | |
| tRx_DQS_DCD_Rj - Applied DCD and Rj RMS to the DQS, Max | |
| VRx_DQS - DQS Rx Input Voltage Sensitivity (differential pp), Max | |
| VIX_DQS_Ratio - DQS differential input crosspoint voltage ratio, Max | |
| VIHdiffDQS - Differential input high measurement level (DQS_t, DQS_c) | |
| VILdiffDQS - Differential input low measurement level (DQS_t, DQS_c) | |
| SRIdiff_DQS - Differential Input Slew Rate for DQS_t, DQS_c | |
| VRx_DQ - Minimum DQ Rx input voltage sensitivity applied around Vref, Max | |
| RxEH_Stressed_Eye_Golden_Ref_Channel_1 - Eye height of stressed eye, Max | |
| RxEH_Stressed_Eye_Golden_Ref_Channel_1 - Eye height, Max | |
| RxEW_Stressed_Eye_Golden_Ref_Channel_1 - Eye width of stressed eye, Max | |
| Vswing_Stressed_Eye_Golden_Ref_Channel_1 - Vswing stress, Max | |
| Sj_Stressed_Eye_Golden_Ref_Channel_1 - Injected sinusoidal jitter at 200 MHz, Min | |
| Sj_Stressed_Eye_Golden_Ref_Channel_1 - Injected sinusoidal jitter at 200 MHz, Max | |
| Rj_Stressed_Eye_Golden_Ref_Channel_1 - Injected Random wide band (10 MHz-1 GHz) Jitter, Min | |
| Rj_Stressed_Eye_Golden_Ref_Channel_1 - Injected Random wide band Jitter, Max | |
| Vnoise_Stressed_Eye_Golden_Ref_Channel_1 - Injected voltage noise (PRBS23 / 2.1 GHz), Min | |
| Vnoise_Stressed_Eye_Golden_Ref_Channel_1 - Injected voltage noise, Max | |
| Golden_Ref_Channel_1_Characteristics | |
| tCT_IS, Min | |
| tCT_Enable, Min | |
| tCT_Valid, Max | |
| VIH(AC)_TEN - TEN AC Input High Voltage, Min | |
| VIH(DC)_TEN - TEN DC Input High Voltage, Min | |
| VIL(DC)_TEN - TEN DC Input Low Voltage, Max | |
| VIL(AC)_TEN - TEN AC Input Low Voltage, Max | |
| TF_input_TEN - TEN Input signal Falling time, Max | |
| TR_input_TEN - TEN Input signal Rising time, Max | |
| VIH(AC)_RESET - AC Input High Voltage, Min | |
| VIH(DC)_RESET - DC Input High Voltage, Min | |
| VIL(DC)_RESET - DC Input Low Voltage, Max | |
| VIL(AC)_RESET - AC Input Low Voltage, Max | |
| TR_RESET - Rising time, Max | |
| tPW_RESET - RESET pulse width, Min | |
| RON34Pu @ VOMdc=0.8*VDDQ, Min | |
| RON34Pu @ VOHdc=0.95*VDDQ, Min | |
| RON48Pd @ VOMdc=0.8*VDDQ, Min | |
| RON48Pd @ VOHdc=0.95*VDDQ, Max | |
| RON48Pu @ VOMdc=0.8*VDDQ, Min | |
| RON48Pu @ VOHdc=0.95*VDDQ, Min | |
| MMPuPd - Mismatch pull-up/pull-down @ VOMdc=0.8*VDDQ, Min | |
| MMPudd - Mismatch DQ-DQ within byte pull-up @ VOMdc=0.8*VDDQ, Max | |
| MMPddd - Mismatch DQ-DQ within byte pull-dn @ VOMdc=0.8*VDDQ, Max | |
| RON34Pd (Loopback) @ VOLdc=0.5*VDDQ, Min | |
| RON34Pd (Loopback) @ VOHdc=0.95*VDDQ, Max | |
| RON34Pu (Loopback) @ VOLdc=0.5*VDDQ, Max | |
| MMPuPd (Loopback) - Mismatch pull-up/pull-down, Min | |
| MMPudd (Loopback) - Mismatch LBDQS-LBDQ pull-up, Max | |
| MMPddd (Loopback) - Mismatch LBDQS-LBDQ pull-dn, Max | |
| tLBQSL - Loopback LBDQS Output Low Time, Min | |
| tLBQSH - Loopback LBDQS Output High Time, Min | |
| tLBDQSQ - Loopback LBDQS to LBDQ Skew, Min | |
| tLBQH - Loopback LBDQ Output Time from LBDQS, Min | |
| tLBDVW - Loopback Data valid window (tLBQH-tLBDQSQ) per UI per DRAM, Min | |
| RONPd (Alert_n) @ VOLdc=0.1*VDDQ, Min | |
| RONPd (Alert_n) @ VOMdc=0.8*VDDQ, Min | |
| RONPd (Alert_n) @ VOHdc=0.95*VDDQ, Min | |
| RONPd_CT @ VOBdc=0.2*VDDQ, Max | |
| RONPd_CT @ VOLdc=0.5*VDDQ, Max | |
| RONPd_CT @ VOMdc=0.8*VDDQ, Max | |
| RONPd_CT @ VOHdc=0.95*VDDQ, Max | |
| RONPu_CT @ VOBdc=0.2*VDDQ, Max | |
| RONPu_CT @ VOLdc=0.5*VDDQ, Max | |
| RONPu_CT @ VOMdc=0.8*VDDQ, Max | |
| RONPu_CT @ VOHdc=0.95*VDDQ, Max | |
| VOH - Output high measurement level (for output SR) | |
| VOL - Output low measurement level (for output SR) | |
| VOH - Output high measurement level (Loopback signals) | |
| VOL - Output low measurement level (Loopback signals) | |
| SRQse - Single ended output slew rate, Min | |
| SRQse - Single ended output slew rate, Max | |
| VOHdiff - Differential output high measurement level (for output SR) | |
| VOLdiff - Differential output low measurement level (for output SR) | |
| SRQdiff - Differential output slew rate, Min | |
| SRQdiff - Differential output slew rate, Max | |
| tTx_DQS_1UI_Rj_NoBUJ - Rj RMS of 1-UI Jitter without BUJ, Max | |
| tTx_DQS_1UI_Dj_NoBUJ - Dj pp Value of 1-UI Jitter without BUJ, Max | |
| tTx_DQS_NUI_Rj_NoBUJ (1<N<4) - Rj RMS of N-UI jitter without BUJ, Max | |
| tTx_DQS_NUI_Dj_NoBUJ (1<N<4) - Dj pp Value of N-UI Jitter without BUJ, Max | |
| tTx_DQ_1UI_Rj_NoBUJ - Rj RMS of 1-UI jitter without BUJ, Max | |
| tTx_DQ_1UI_Dj_NoBUJ - Dj pp 1-UI jitter without BUJ, Max | |
| tTx_DQ_NUI_Rj_NoBUJ (1<N<4) - Rj RMS of N-UI jitter without BUJ, Max | |
| tTx_DQ_NUI_Dj_NoBUJ (1<N<4) - Dj pp N-UI jitter without BUJ, Max | |
| tTx_DQS2DQ - Delay of any data lane relative to strobe lane, Min | |
| tTx_DQS2DQ - Delay of any data lane relative to strobe lane, Max | |
| TxEH_DQ_SES_1UI - Eye Height (skew DQ/DQS 1UI), Min | |
| TxEW_DQ_SES_1UI - Eye Width (skew DQ/DQS 1UI), Min | |
| TxEH_DQ_SES_2UI - Eye Height (skew DQ/DQS 2UI), Min | |
| TxEW_DQ_SES_2UI - Eye Width (skew DQ/DQS 2UI), Min | |
| TxEH_DQ_SES_3UI - Eye Height (skew DQ/DQS 3UI), Min | |
| TxEW_DQ_SES_3UI - Eye Width (skew DQ/DQS 3UI), Min | |
| TxEH_DQ_SES_4UI - Eye Height (skew DQ/DQS 4UI), Min | |
| TxEW_DQ_SES_4UI - Eye Width (skew DQ/DQS 4UI), Min | |
| TxEH_DQ_SES_5UI - Eye Height (skew DQ/DQS 5UI), Min | |
| TxEW_DQ_SES_5UI - Eye Width (skew DQ/DQS 5UI), Min | |
| MID-LEVEL definition for IDD/IPP/IDDQ measurement | |
| TCASE for IDD/IPP/IDDQ measurement | |
| Burst Length (BL) for IDD patterns | |
| IDD0 current definition | |
| IDDQ0 current definition | |
| IPP0 current definition | |
| IDD0F current definition | |
| IDD2N current definition | |
| IDD2NT current definition | |
| IDD2P current definition | |
| IDD3N current definition | |
| IDD3P current definition | |
| IDD4R current definition | |
| IDD4RC current definition | |
| IDD4W current definition | |
| IDD4WC current definition | |
| IDD5B current definition | |
| IDD5F current definition | |
| IDD5C current definition | |
| IDD6N current definition | |
| IDD6E current definition | |
| IDD7 current definition | |
| IDD8 current definition | |
| IDD9 (Optional) current definition | |
| Overall module length (outer) | |
| Overall module length (inner) | |
| Notch / inner height dimension | |
| Front lower dimension (left segment) | |
| Front lower dimension (right segment) | |
| Top-left small dimension | |
| Edge dimension with tolerance | |
| Edge dimension with tolerance (lower) | |
| Top corner dimension | |
| Detail E callout dimension | |
| Back side height dimension with tolerance | |
| Side view contact pitch | |
| Side view max dimension | |
| Notch / corner radius | |
| Detail B / D dimension | |
| Contacts A/F dimension | |
| Contacts A/F dimension with tolerance | |
| Contacts E dimension with tolerance | |
| Contacts B keep-out note | |
| Contacts B keep-out max dimension | |
| Contacts D dimension with tolerance | |
| Contacts D keep-out note | |
| Contacts D keep-out max dimension | |
| Detail F dimension with tolerance | |
| Module density / configuration | |
| Date | |
| Bank (x4/x8) | |
| Bank (x16) | |
| Burst Length | |
| Module organization | |
| Register / RCD present | |
| DRAM placement count (page1 diagram) | |
| Resistor value note | |
| DRAM placement diagram (page2) | |
| DRAM ZQ pin resistor note | |
| tREFI1 REFab Normal, 0°C<=TCASE<=85°C | |
| tREFI1 REFab Normal, 85°C<TCASE<=95°C | |
| tREFI2 REFab Fine Granularity, 0°C<=TCASE<=85°C | |
| tREFI2 REFab Fine Granularity, 85°C<TCASE<=95°C | |
| tREFIsb REFsb Fine Granularity, 0°C<=TCASE<=85°C | |
| tREFIsb REFsb Fine Granularity, 85°C<TCASE<=95°C | |
| Device Supply Voltage VDD (Recommended DC Operating) | |
| VDD Z(f) Spec Freq 2MHz to 10MHz (Zmax) | |
| VDD Z(f) Spec Freq 20MHz (Zmax) | |
| Supply Voltage for I/O VDDQ (Recommended DC Operating) | |
| VDDQ Z(f) Spec Freq 2MHz to 10MHz (Zmax) | |
| VDDQ Z(f) Spec Freq 20MHz (Zmax) | |
| Core Power Voltage VPP (Recommended DC Operating) | |
| VPP Z(f) Spec Freq 2MHz to 10MHz (Zmax) | |
| VPP Z(f) Spec Freq 20MHz (Zmax) | |
| Rx Mask voltage p-p (VciVW) DDR5-3200 (Max) | |
| Rx Mask voltage p-p (VciVW) DDR5-3600 (Max) | |
| Rx Mask voltage p-p (VciVW) DDR5-4000 (Max) | |
| Rx Mask voltage p-p (VciVW) DDR5-4400 (Max) | |
| Rx Mask voltage p-p (VciVW) DDR5-4800 (Max) | |
| Rx Timing Window (TcIVW) DDR5-3200 to 4800 (Max) | |
| CA Input Pulse Amplitude (VIHL_AC) DDR5-3200 to 4000 | |
| CA Input Pulse Amplitude (VIHL_AC) DDR5-4400 to 4800 | |
| CA Input Pulse Width (TcIPW) DDR5-3200 to 4800 | |
| Input Slew Rate over VcIVW (SRIN_cIVW) DDR5-3200 to 4800 (Min) | |
| Input Slew Rate over VcIVW (SRIN_cIVW) DDR5-3200 to 4800 (Max) | |
| DRAM Reference clock frequency (tCK) DDR5-3200..4800 (Min) | |
| DRAM Reference clock frequency (tCK) DDR5-3200..4800 (Max) | |
| Duty Cycle Error (tCK_Duty_UI_Error) DDR5-3200..4400 (Max) | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) DDR5-3200..4800 (Max) | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) DDR5-3200..4800 (Max) | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) DDR5-3200..4800 (Max) | |
| Rj RMS value of N-UI Jitter, N=2,3 (tCK_NUI_Rj_NoBUJ) DDR5-3200..4800 (Max) | |
| Dj pp value of N-UI Jitter, N=2,3 (tCK_NUI_Dj_NoBUJ) DDR5-3200..4800 (Max) | |
| Tj value of N-UI Jitter, N=2,3 (tCK_NUI_Tj_NoBUJ) DDR5-3200..4800 (Max) | |
| Rj RMS value of N-UI Jitter, N=4..30 (tCK_NUI_Rj_NoBUJ) DDR5-3200..4800 (Max) | |
| Dj pp value of N-UI Jitter, N=4..30 (tCK_NUI_Dj_NoBUJ) DDR5-3200..4800 (Max) | |
| Tj value of N-UI Jitter, N=4..30 (tCK_NUI_Tj_NoBUJ) DDR5-3200..4800 (Max) | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) DDR5-3200..4800 (Max) | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) DDR5-6800..8400 (Max) | |
| Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-3200 (Max) | |
| Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-3600 (Max) | |
| Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-4000 (Max) | |
| Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-4400 (Max) | |
| Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-4800 (Max) | |
| Differential input high measurement level CK (VIHdiffCK) DDR5-3200..6400 | |
| Differential input low measurement level CK (VILdiffCK) DDR5-3200..6400 | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) DDR5-3200..4800 (Min) | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) DDR5-3200..4800 (Max) | |
| DQ Timing Width (tRx_DQ_tMargin) DDR5-3200 (Min) | |
| DQ Timing Width (tRx_DQ_tMargin) DDR5-3600 (Min) | |
| DQ Timing Width (tRx_DQ_tMargin) DDR5-4000 (Min) | |
| DQ Timing Width (tRx_DQ_tMargin) DDR5-4400 (Min) | |
| DQ Timing Width (tRx_DQ_tMargin) DDR5-4800 (Min) | |
| Degradation of timing width with DCD injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD) DDR5-3200..4800 (Max) | |
| Degradation of timing width with Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_Rj) DDR5-3200..4800 (Max) | |
| Degradation of timing width with both DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) DDR5-3200..4800 (Max) | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-3200..4000 (Min) | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-3200 (Max) | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-3600 (Max) | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-4000 (Max) | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-4400 (Max) | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-4800 (Max) | |
| Applied DCD to the DQS (tRx_DQS_DCD) DDR5-3200..4800 (Max) | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) DDR5-3200..4800 (Max) | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) DDR5-3200..4800 (Max) | |
| DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-3200 (Max) | |
| DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-3600 (Max) | |
| DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-4000 (Max) | |
| DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-4400 (Max) | |
| DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-4800 (Max) | |
| DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) DDR5-3200..4800 (Max) | |
| Differential input high measurement level DQS (VIHdiffDQS) DDR5-3200..6400 | |
| Differential input low measurement level DQS (VILdiffDQS) DDR5-3200..6400 | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) DDR5-3200..4800 | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-3200 (Max) | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-3600 (Max) | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-4000 (Max) | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-4400-6400 (Max) | |
| Eye height of stressed eye for Golden Reference Channel 1 DDR5-3200 (Max) | |
| Eye height of stressed eye for Golden Reference Channel 1 DDR5-3600 (Max) | |
| Eye height of stressed eye for Golden Reference Channel 1 DDR5-4000 (Max) | |
| Eye height of stressed eye for Golden Reference Channel 1 DDR5-4400 (Max) | |
| Eye height of stressed eye for Golden Reference Channel 1 DDR5-4800 (Max) | |
| Eye width of stressed eye Golden Reference Channel 1 DDR5-3200..4800 (Max) | |
| Vswing stress to meet above data eye DDR5-3200..4800 (Max) | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye DDR5-3200..4800 (Min) | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye DDR5-3200..4800 (Max) | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye DDR5-3200..4800 (Min) | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye DDR5-3200..4800 (Max) | |
| Injected voltage noise (PRBS23 / at 2.1 GHz) to meet above data eye DDR5-3200..4800 (Min) | |
| Injected voltage noise (PRBS23 / at 2.1 GHz) to meet above data eye DDR5-3200..4800 (Max) | |
| Golden Reference Channel 1 Characteristics DDR5-3200..4800 | |
| DFE tap range limit | |
| Minimum BER requirement for stressed eye | |
| Connectivity Test Mode tCT_IS (Min) | |
| Connectivity Test Mode tCT_Enable (Min) | |
| Connectivity Test Mode tCT_Valid (Max) | |
| TEN AC Input High Voltage (VIH(AC)_TEN) (Min) | |
| TEN AC Input High Voltage (VIH(AC)_TEN) (Max) | |
| TEN DC Input High Voltage (VIH(DC)_TEN) (Min) | |
| TEN DC Input High Voltage (VIH(DC)_TEN) (Max) | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) (Min) | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) (Max) | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) (Min) | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) (Max) | |
| TEN Input signal Falling time (TF_input_TEN) (Max) | |
| TEN Input signal Rising time (TR_input_TEN) (Max) | |
| RESET_n AC Input High Voltage (VIH(AC)_RESET) (Min) | |
| RESET_n AC Input High Voltage (VIH(AC)_RESET) (Max) | |
| RESET_n DC Input High Voltage (VIH(DC)_RESET) (Min) | |
| RESET_n DC Input High Voltage (VIH(DC)_RESET) (Max) | |
| RESET_n DC Input Low Voltage (VIL(DC)_RESET) (Min) | |
| RESET_n DC Input Low Voltage (VIL(DC)_RESET) (Max) | |
| RESET_n AC Input Low Voltage (VIL(AC)_RESET) (Min) | |
| RESET_n AC Input Low Voltage (VIL(AC)_RESET) (Max) | |
| RESET_n Rising time (TR_RESET) (Max) | |
| RESET pulse width (tPW_RESET) (Min) | |
| Table 20 assumptions | |
| RON34Pd Min @ VOLdc=0.5*VDDQ | |
| RON34Pd Nom @ VOLdc=0.5*VDDQ | |
| RON34Pd Max @ VOLdc=0.5*VDDQ | |
| RON34Pd Min @ VOMdc=0.8*VDDQ | |
| RON34Pd Nom @ VOMdc=0.8*VDDQ | |
| RON34Pd Max @ VOMdc=0.8*VDDQ | |
| RON34Pd Min @ VOHdc=0.95*VDDQ | |
| RON34Pd Nom @ VOHdc=0.95*VDDQ | |
| RON34Pd Max @ VOHdc=0.95*VDDQ | |
| RON34Pu Min @ VOLdc=0.5*VDDQ | |
| RON34Pu Nom @ VOLdc=0.5*VDDQ | |
| RON34Pu Max @ VOLdc=0.5*VDDQ | |
| RON34Pu Min @ VOMdc=0.8*VDDQ | |
| RON34Pu Nom @ VOMdc=0.8*VDDQ | |
| RON34Pu Max @ VOMdc=0.8*VDDQ | |
| RON34Pu Min @ VOHdc=0.95*VDDQ | |
| RON34Pu Nom @ VOHdc=0.95*VDDQ | |
| RON34Pu Max @ VOHdc=0.95*VDDQ | |
| RON48Pd Min @ VOLdc=0.5*VDDQ | |
| RON48Pd Nom @ VOLdc=0.5*VDDQ | |
| RON48Pd Max @ VOLdc=0.5*VDDQ | |
| RON48Pd Min @ VOMdc=0.8*VDDQ | |
| RON48Pd Nom @ VOMdc=0.8*VDDQ | |
| RON48Pd Max @ VOMdc=0.8*VDDQ | |
| RON48Pd Min @ VOHdc=0.95*VDDQ | |
| RON48Pd Nom @ VOHdc=0.95*VDDQ | |
| RON48Pd Max @ VOHdc=0.95*VDDQ | |
| RON48Pu Min @ VOLdc=0.5*VDDQ | |
| RON48Pu Nom @ VOLdc=0.5*VDDQ | |
| RON48Pu Max @ VOLdc=0.5*VDDQ | |
| RON48Pu Min @ VOMdc=0.8*VDDQ | |
| RON48Pu Nom @ VOMdc=0.8*VDDQ | |
| RON48Pu Max @ VOMdc=0.8*VDDQ | |
| RON48Pu Min @ VOHdc=0.95*VDDQ | |
| RON48Pu Nom @ VOHdc=0.95*VDDQ | |
| RON48Pu Max @ VOHdc=0.95*VDDQ | |
| Mismatch pull-up/pull-down MMPuPd Min @ VOMdc=0.8*VDDQ | |
| Mismatch pull-up/pull-down MMPuPd Max @ VOMdc=0.8*VDDQ | |
| Mismatch DQ-DQ within byte pull-up MMPudd Max @ VOMdc=0.8*VDDQ | |
| Mismatch DQ-DQ within byte pull-dn MMPddd Max @ VOMdc=0.8*VDDQ | |
| Loopback driver supported impedance | |
| LB RON34Pd Min @ VOLdc=0.5*VDDQ | |
| LB RON34Pd Nom @ VOLdc=0.5*VDDQ | |
| LB RON34Pd Max @ VOLdc=0.5*VDDQ | |
| LB RON34Pd Min @ VOMdc=0.8*VDDQ | |
| LB RON34Pd Nom @ VOMdc=0.8*VDDQ | |
| LB RON34Pd Max @ VOMdc=0.8*VDDQ | |
| LB RON34Pd Min @ VOHdc=0.95*VDDQ | |
| LB RON34Pd Nom @ VOHdc=0.95*VDDQ | |
| LB RON34Pd Max @ VOHdc=0.95*VDDQ | |
| LB RON34Pu Min @ VOLdc=0.5*VDDQ | |
| LB RON34Pu Nom @ VOLdc=0.5*VDDQ | |
| LB RON34Pu Max @ VOLdc=0.5*VDDQ | |
| LB RON34Pu Min @ VOMdc=0.8*VDDQ | |
| LB RON34Pu Nom @ VOMdc=0.8*VDDQ | |
| LB RON34Pu Max @ VOMdc=0.8*VDDQ | |
| LB RON34Pu Min @ VOHdc=0.95*VDDQ | |
| LB RON34Pu Nom @ VOHdc=0.95*VDDQ | |
| LB RON34Pu Max @ VOHdc=0.95*VDDQ | |
| LB Mismatch pull-up/pull-down MMPuPd Min @ VOMdc=0.8*VDDQ | |
| LB Mismatch pull-up/pull-down MMPuPd Max @ VOMdc=0.8*VDDQ | |
| LB Mismatch LBDQS-LBDQ within device pull-up MMPudd Max | |
| LB Mismatch LBDQS-LBDQ within device pull-dn MMPddd Max | |
| Alert_n RONPd Min @ VOLdc=0.1*VDDQ | |
| Alert_n RONPd Max @ VOLdc=0.1*VDDQ | |
| Alert_n RONPd Min @ VOMdc=0.8*VDDQ | |
| Alert_n RONPd Max @ VOMdc=0.8*VDDQ | |
| Alert_n RONPd Min @ VOHdc=0.95*VDDQ | |
| Alert_n RONPd Max @ VOHdc=0.95*VDDQ | |
| CT RONPd_CT Max @ VOBdc=0.2xVDDQ | |
| CT RONPd_CT Max @ VOLdc=0.5xVDDQ | |
| CT RONPd_CT Max @ VOMdc=0.8xVDDQ | |
| CT RONPd_CT Max @ VOHdc=0.95xVDDQ | |
| CT RONPu_CT Max @ VOBdc=0.2xVDDQ | |
| CT RONPu_CT Max @ VOLdc=0.5xVDDQ | |
| CT RONPu_CT Max @ VOMdc=0.8xVDDQ | |
| CT RONPu_CT Max @ VOHdc=0.95xVDDQ | |
| VOH Output high measurement level (Loopback, for output SR) | |
| VOL Output low measurement level (Loopback, for output SR) | |
| tTx_DQS_1UI_Rj_NoBUJ Max (Rj RMS 1-UI without BUJ) | |
| tTx_DQS_1UI_Dj_NoBUJ Max (Dj pp 1-UI without BUJ) | |
| tTx_DQS_NUI_Rj_NoBUJ Max (Rj RMS N-UI without BUJ, 1<N<4) | |
| tTx_DQS_NUI_Dj_NoBUJ Max (Dj pp N-UI without BUJ, 1<N<4) | |
| Tx DQS Rj max alt value note | |
| tTx_DQ_1UI_Rj_NoBUJ Max (Rj RMS 1-UI without BUJ) | |
| tTx_DQ_1UI_Dj_NoBUJ Max (Dj pp 1-UI without BUJ) | |
| tTx_DQ_NUI_Rj_NoBUJ Max (Rj RMS N-UI without BUJ, 1<N<4) | |
| tTx_DQ_NUI_Dj_NoBUJ Max (Dj pp N-UI without BUJ, 1<N<4) | |
| Tx DQ Rj max alt value note | |
| TxEH_DQ_SES_1UI Eye Height @ DQ-DQS skew 1UI Min | |
| TxEW_DQ_SES_1UI Eye Width @ DQ-DQS skew 1UI Min | |
| TxEH_DQ_SES_2UI Eye Height @ DQ-DQS skew 2UI Min | |
| TxEW_DQ_SES_2UI Eye Width @ DQ-DQS skew 2UI Min | |
| TxEH_DQ_SES_3UI Eye Height @ DQ-DQS skew 3UI Min | |
| TxEW_DQ_SES_3UI Eye Width @ DQ-DQS skew 3UI Min | |
| TxEH_DQ_SES_4UI Eye Height @ DQ-DQS skew 4UI Min | |
| TxEW_DQ_SES_4UI Eye Width @ DQ-DQS skew 4UI Min | |
| TxEH_DQ_SES_5UI Eye Height @ DQ-DQS skew 5UI Min | |
| TxEW_DQ_SES_5UI Eye Width @ DQ-DQS skew 5UI Min | |
| Tx DQ Stressed Eye BER/Confidence condition | |
| Overall length (Front, outer) | |
| Length (Front, inner) | |
| Module height (overall) | |
| Height (sub) | |
| Dimension | |
| Thickness / edge dimension | |
| Dimension (Detail E) | |
| Notch / key length (Back) | |
| Pin callout | |
| Component callout dimension | |
| Detail A dimension (max) | |
| Detail of Contacts A, F | |
| Detail of Contacts B - pin callout | |
| Detail of Contacts B | |
| Detail of Contacts C - pin callout | |
| Detail of Contacts C | |
| Detail of Contacts D | |
| Detail of Contacts E | |
| Non-metallized keep out area | |
| Units note | |
| Base die | |
| Notice | |
| Temperature Encoding | |
| Same Bank Refresh | |
| VrefDQ / VrefCA / VrefCS Training | |
| Post Package Repair | |
| Input Clock Frequency Change | |
| Maximum Power Saving Mode (MPSM) | |
| Multi-Purpose Command (MPC) | |
| Per DRAM Addressability (PDA) | |
| Read Training Mode | |
| CA Training Mode | |
| CS Training Mode | |
| Per Pin VREFDQ Training | |
| Write Leveling Training Mode | |
| Connectivity Test (CT) | |
| ZQ Calibration | |
| DFE for DQ | |
| DQS Interval Oscillator | |
| 1N / 2N Mode support for Commands | |
| ECC Transparency and Error Scrub | |
| CRC (Cyclic Redundancy Check) | |
| Loopback | |
| Package Output Driver Test Mode | |
| Training Modes | |
| CA0_A - CA6_A | |
| CA0_B - CA6_B | |
| CS0_A_n - CS1_A_n | |
| CS0_B_n - CS1_B_n | |
| DQ0_B - DQ31_B | |
| CB0_A - CB7_A | |
| CB0_B - CB7_B | |
| TDQS0_A_t-TDQS9_A_t | |
| TDQS0_B_t-TDQS9_B_t | |
| TDQS0_A_c-TDQS9_A_c | |
| TDQS0_B_c-TDQS9_B_c | |
| DQS0_A_t - DQS9_A_t | |
| DQS0_B_t - DQS9_B_t | |
| DQS0_A_c - DQS9_A_c | |
| DQS0_B_c - DQS9_B_c | |
| PAR_A | |
| PAR_B | |
| RSP_A_n | |
| RSP_B_n | |
| VSS | |
| PWR_GOOD /FAIL_n | |
| SCL | |
| ALERT_n | |
| SDA | |
| RESET_n | |
| SAA | |
| LBD | |
| CK_t | |
| LBS | |
| CK_c | |
| RFU | |
| I/O Function: CK_t, CK_c | |
| I/O Function: CA0_A - CA6_A, CA0_B - CA6_B, PAR_A, PAR_B | |
| I/O Function: CS0_A_n - CS1_A_n, CS0_B_n - CS1_B_n | |
| I/O Function: DQ0_A - DQ31_A, DQ0_B - DQ31_B | |
| I/O Function: CB0_A - CB7_A, CB0_B - CB7_B | |
| I/O Function: DQS0_A_t - DQS9_A_t, DQS0_A_c - DQS9_A_c, DQS0_B_t - DQS9_B_t, DQS0_B_c - DQS9_B_c | |
| I/O Function: TDQS0_A_c-DQS9_A_c, TDQS0_B_c-DQS9_B_c | |
| I/O Function: DM0_A_n-DM3_A_n, DM0_B_n-DM3_B_n | |
| I/O Function: LBDQ | |
| I/O Function: LBDQS | |
| I/O Function: ALERT_n | |
| I/O Function: RESET_n | |
| I/O Function: SCL | |
| I/O Function: SDA | |
| I/O Function: SAA | |
| I/O Function: RFU | |
| I/O Function: PWR_GOOD | |
| I/O Function: VIN_MGMT | |
| I/O Function: VIN_BULK | |
| I/O Function: VSS | |
| Pin assignment - KEY position | |
| drawing_title | |
| module_organization | |
| register_block | |
| register_output_signal | |
| register_input_signal | |
| dram_device_placement | |
| note | |
| dram_data_wiring_signal | |
| dram_device_label | |
| Supported Frequency Down Bin 3200C | |
| Supported Frequency Down Bin 3200BN/3200B | |
| Supported Frequency Down Bin 3200AN | |
| Supported Frequency Down Bin 3600C | |
| Supported Frequency Down Bin 3600BN/3600B | |
| Supported Frequency Down Bin 3600AN | |
| Supported Frequency Down Bin 4000C | |
| Supported Frequency Down Bin 4000BN/4000B | |
| Supported Frequency Down Bin 4000AN | |
| Supported Frequency Down Bin 4400C | |
| Supported Frequency Down Bin 4400BN/4400B | |
| Supported Frequency Down Bin 4400AN | |
| Supported Frequency Down Bin (default 4400B base) tCK(AVG) | |
| Supported Frequency Down Bin 4800C | |
| Supported Frequency Down Bin 4800BN | |
| Supported Frequency Down Bin 4800B | |
| Supported Frequency Down Bin 4800AN | |
| Supported Frequency Down Bin (default base) tCK(AVG) | |
| PCB overall length (outer) | |
| PCB length (inner) | |
| PCB overall height | |
| Height to notch / contact area | |
| Contact field length dimension | |
| Edge offset dimension | |
| Top edge thickness / step dimension | |
| Corner notch dimension | |
| Contact thickness | |
| Contact width | |
| Contact dimension | |
| Keep out area dimension | |
| Detail callout | |
| Number of ranks | |
| Number of Bank Groups | |
| Block diagram title / module configuration | |
| Central component (block diagram) | |
| Register input - command/address | |
| Register input - chip select | |
| Register input - parity | |
| Register input - clock true | |
| Register input - clock complement | |
| Register input - reset | |
| Register input - QLBD | |
| Register input - QLBS | |
| Register input - alert | |
| Register output A-side command/address | |
| Register output A-side chip select | |
| Register output B-side command/address | |
| DRAM device width | |
| DRAM data byte routing - A side | |
| Command/address bus A (page2 diagram) | |
| DRAM data byte routing - B side | |
| Command/address bus B (page2 diagram) | |
| DRAM ZQ resistor note | |
| Voltage on VDD pin relative to Vss (Absolute Maximum DC Rating) | |
| Voltage on VDDQ pin relative to Vss (Absolute Maximum DC Rating) | |
| Voltage on VPP pin relative to Vss (Absolute Maximum DC Rating) | |
| Voltage on any pin relative to Vss (Absolute Maximum DC Rating) | |
| Storage Temperature (Absolute Maximum DC Rating) | |
| Device Supply Voltage VDD (Recommended DC Operating) Min. | |
| Device Supply Voltage VDD (Recommended DC Operating) Typ. | |
| Device Supply Voltage VDD (Recommended DC Operating) Max. | |
| Device Supply Voltage VDD Z(f) Spec Freq: 2MHz to 10MHz Zmax | |
| Device Supply Voltage VDD Z(f) Spec Freq: 20MHz Zmax | |
| Supply Voltage for I/O VDDQ (Recommended DC Operating) Min. | |
| Supply Voltage for I/O VDDQ (Recommended DC Operating) Typ. | |
| Supply Voltage for I/O VDDQ (Recommended DC Operating) Max. | |
| Supply Voltage for I/O VDDQ Z(f) Spec Freq: 2MHz to 10MHz Zmax | |
| Supply Voltage for I/O VDDQ Z(f) Spec Freq: 20MHz Zmax | |
| Core Power Voltage VPP (Recommended DC Operating) Min. | |
| Core Power Voltage VPP (Recommended DC Operating) Typ. | |
| Core Power Voltage VPP (Recommended DC Operating) Max. | |
| Core Power Voltage VPP Z(f) Spec Freq: 2MHz to 10MHz Zmax | |
| Core Power Voltage VPP Z(f) Spec Freq: 20MHz Zmax | |
| Section title | |
| Supported Frequency Down Bins - reference tAAmin | |
| Supported Frequency Down Bins - reference Read CL/Write CWL | |
| Supported Frequency Down Bins - reference tCK(AVG) min | |
| Supported Frequency Down Bins - reference tCK(AVG) max | |
| Down bin 3200C tAAmin | |
| Down bin 3200C tRCDmin/tRPmin | |
| Down bin 3200C Read CL/Write CWL | |
| Down bin 3200C tCK(AVG) min | |
| Down bin 3200C tCK(AVG) max | |
| Down bin 3200BN / 3200B tAAmin | |
| Down bin 3200BN / 3200B tRCDmin/tRPmin | |
| Down bin 3200BN / 3200B Read CL/Write CWL | |
| Down bin 3200BN / 3200B tCK(AVG) min | |
| Down bin 3200BN / 3200B tCK(AVG) max | |
| Down bin 3200AN tAAmin | |
| Down bin 3200AN tRCDmin/tRPmin | |
| Down bin 3200AN Read CL/Write CWL | |
| Down bin 3200AN tCK(AVG) | |
| Down bin 3600C tAAmin | |
| Down bin 3600C tRCDmin/tRPmin | |
| Down bin 3600C Read CL/Write CWL | |
| Down bin 3600C tCK(AVG) min | |
| Down bin 3600C tCK(AVG) max | |
| Down bin 3600BN / 3600B tAAmin | |
| Down bin 3600BN / 3600B tRCDmin/tRPmin | |
| Down bin 3600BN / 3600B Read CL/Write CWL | |
| Down bin 3600BN / 3600B tCK(AVG) min | |
| Down bin 3600BN / 3600B tCK(AVG) max | |
| Down bin 3600AN tAAmin | |
| Down bin 3600AN tRCDmin/tRPmin | |
| Down bin 3600AN Read CL/Write CWL | |
| Down bin 3600AN tCK(AVG) | |
| Down bin 4000C tAAmin | |
| Down bin 4000C tRCDmin/tRPmin | |
| Down bin 4000C Read CL/Write CWL | |
| Down bin 4000C tCK(AVG) min | |
| Down bin 4000C tCK(AVG) max | |
| Down bin 4000BN / 4000B tAAmin | |
| Down bin 4000BN / 4000B tRCDmin/tRPmin | |
| Down bin 4000BN / 4000B Read CL/Write CWL | |
| Down bin 4000BN / 4000B tCK(AVG) min | |
| Down bin 4000BN / 4000B tCK(AVG) max | |
| Down bin 4000AN tAAmin | |
| Down bin 4000AN tRCDmin/tRPmin | |
| Down bin 4000AN Read CL/Write CWL | |
| Down bin 4000AN tCK(AVG) | |
| Down bin 4400C tAAmin | |
| Down bin 4400C tRCDmin/tRPmin | |
| Down bin 4400C Read CL/Write CWL | |
| Down bin 4400C tCK(AVG) min | |
| Down bin 4400C tCK(AVG) max | |
| Down bin 4400BN / 4400B tAAmin | |
| Down bin 4400BN / 4400B tRCDmin/tRPmin | |
| Down bin 4400BN / 4400B Read CL/Write CWL | |
| Down bin 4400BN / 4400B tCK(AVG) min | |
| Down bin 4400BN / 4400B tCK(AVG) max | |
| Down bin 4400AN tAAmin | |
| Down bin 4400AN tRCDmin/tRPmin | |
| Down bin 4400AN Read CL/Write CWL | |
| Down bin 4400AN tCK(AVG) | |
| Down bin 4800C tAAmin | |
| Down bin 4800C tRCDmin/tRPmin | |
| Down bin 4800C Read CL/Write CWL | |
| Down bin 4800C tCK(AVG) min | |
| Down bin 4800C tCK(AVG) max | |
| Down bin 4800BN tAAmin | |
| Down bin 4800BN tRCDmin/tRPmin | |
| Down bin 4800BN Read CL/Write CWL | |
| Down bin 4800BN tCK(AVG) min | |
| Down bin 4800BN tCK(AVG) max | |
| Down bin 4800B tAAmin | |
| Down bin 4800B tRCDmin/tRPmin | |
| Down bin 4800B Read CL/Write CWL | |
| Down bin 4800B tCK(AVG) min | |
| Down bin 4800B tCK(AVG) max | |
| Down bin 4800AN tAAmin | |
| Down bin 4800AN tRCDmin/tRPmin | |
| Down bin 4800AN Read CL/Write CWL | |
| Down bin 4800AN tCK(AVG) | |
| drawing units | |
| overall length (Front, outer) | |
| length (Front, inner) | |
| edge feature width (top-left) | |
| right-edge feature width | |
| module height (overall) | |
| height dimension | |
| key/notch offset from left | |
| contact span left of key | |
| contact span right of key | |
| 3.00 dimension (left edge) | |
| 3.35 dimension (top-left detail) | |
| pin label (front, left start) | |
| pin label | |
| component label (front center) | |
| detail callouts on front | |
| component label (TS) | |
| back contact-set offset | |
| component label (Back center) | |
| Side view thickness | |
| Side view thickness qualifier | |
| fillet radius (Detail A) | |
| left datum dimension (Detail A) | |
| datum dimension (Detail A) | |
| contact pitch (Detail of Contacts A, F) | |
| contact height (Detail of Contacts A, F) | |
| contact spacing (Detail of Contacts A, F) | |
| non-metalized keep-out (Detail of Contacts A, F) | |
| keep-out note (Detail of Contacts A, F) | |
| pin label (Detail of Contacts B) | |
| contact height (Detail of Contacts B) | |
| contact span (Detail of Contacts B) | |
| contact span outer (Detail of Contacts B) | |
| pin label (Detail of Contacts C) | |
| contact height (Detail of Contacts C) | |
| contact height secondary (Detail of Contacts C) | |
| contact span (Detail of Contacts C) | |
| contact span outer (Detail of Contacts C) | |
| contact pitch (Detail of Contacts D) | |
| contact height (Detail of Contacts D) | |
| contact spacing (Detail of Contacts D) | |
| non-metalized keep-out (Detail of Contacts D) | |
| keep-out note (Detail of Contacts D) | |
| datum dimension (Detail of Contacts E) | |
| height dimension (Detail of Contacts E) | |
| contact offset (Detail of Contacts E) | |
| contact width (Detail of Contacts E) | |
| contact span (Detail of Contacts E) | |
| Block diagram title | |
| Register input - host command/address | |
| Register input - loopback data | |
| Register input - loopback strobe | |
| Register output A-side chip select 0 | |
| Register output A-side clock ACK | |
| Register output A-side clock CCK | |
| Register output A-side chip select B 0 | |
| Register output A-side reset | |
| Register output A-side error in | |
| Register output A-side loopback data | |
| Register output A-side loopback strobe | |
| Register output B-side chip select 0 | |
| Register output B-side clock ACK | |
| Register output B-side clock CCK | |
| Register output B-side chip select B 0 | |
| Register output B-side reset | |
| Register output B-side error in | |
| Register output B-side loopback data | |
| Register output B-side loopback strobe | |
| Front-side DRAM placement (A group) | |
| Back-side DRAM placement (A group) | |
| DRAM resistor note | |
| Front A-side DRAM lane block | |
| Front A-side command/address net | |
| Front DQS/DQ lane - DQS5 / DQ[7:4] | |
| Front DQS/DQ lane - DQS6 / DQ[15:12] | |
| Front DQS/DQ lane - DQS7 / DQ[23:20] | |
| Front DQS/DQ lane - DQS8 / DQ[31:28] | |
| Front DQS/DQ lane - DQS9 / CB[7:4] | |
| Front DQS/DQ lane - DQS0 / DQ[3:0] | |
| Front DQS/DQ lane - DQS1 / DQ[11:8] | |
| Front DQS/DQ lane - DQS2 / DQ[19:16] | |
| Front DQS/DQ lane - DQS3 / DQ[27:24] | |
| Front DQS/DQ lane - DQS4 / CB[3:0] | |
| Back B-side DRAM lane block | |
| Back B-side command/address net | |
| Back DQS/DQ lane - DQS9 / CB[7:4] | |
| Back DQS/DQ lane - DQS0 / DQ[3:0] | |
| Back DQS/DQ lane - DQS1 / DQ[11:8] | |
| Back DQS/DQ lane - DQS2 / DQ[19:16] | |
| Back DQS/DQ lane - DQS3 / DQ[27:24] | |
| Back DQS/DQ lane - DQS4 / CB[3:0] | |
| Back DQS/DQ lane - DQS5 / DQ[7:4] | |
| Back DQS/DQ lane - DQS6 / DQ[15:12] | |
| Back DQS/DQ lane - DQS7 / DQ[23:20] | |
| Back DQS/DQ lane - DQS8 / DQ[31:28] | |
| VDD - Voltage on VDD pin relative to Vss (Absolute Maximum DC Rating) | |
| VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Maximum DC Rating) | |
| VPP - Voltage on VPP pin relative to Vss (Absolute Maximum DC Rating) | |
| VIN, VOUT - Voltage on any pin relative to Vss (Absolute Maximum DC Rating) | |
| TSTG - Storage Temperature (Absolute Maximum DC Rating) | |
| tREFI1 - REFab Normal, 0°C <= TCASE <= 85°C | |
| tREFI1 - REFab Normal, 85°C < TCASE <= 95°C | |
| tREFI2 - REFab Fine Granularity, 0°C <= TCASE <= 85°C | |
| tREFI2 - REFab Fine Granularity, 85°C < TCASE <= 95°C | |
| tREFIsb - REFsb Fine Granularity, 0°C <= TCASE <= 85°C | |
| tREFIsb - REFsb Fine Granularity, 85°C < TCASE <= 95°C | |
| VDD - Device Supply Voltage (Recommended DC Operating, Min.) | |
| VDD - Device Supply Voltage (Recommended DC Operating, Typ.) | |
| VDD - Device Supply Voltage (Recommended DC Operating, Max.) | |
| VDD - Z(f) Spec Zmax, Freq: 2MHz to 10MHz (Recommended DC Operating) | |
| VDD - Z(f) Spec Zmax, Freq: 20MHz (Recommended DC Operating) | |
| VDDQ - Supply Voltage for I/O (Recommended DC Operating, Min.) | |
| VDDQ - Supply Voltage for I/O (Recommended DC Operating, Typ.) | |
| VDDQ - Supply Voltage for I/O (Recommended DC Operating, Max.) | |
| VDDQ - Z(f) Spec Zmax, Freq: 2MHz to 10MHz (Recommended DC Operating) | |
| VDDQ - Z(f) Spec Zmax, Freq: 20MHz (Recommended DC Operating) | |
| VPP - Core Power Voltage (Recommended DC Operating, Min.) | |
| VPP - Core Power Voltage (Recommended DC Operating, Typ.) | |
| VPP - Core Power Voltage (Recommended DC Operating, Max.) | |
| VPP - Z(f) Spec Zmax, Freq: 2MHz to 10MHz (Recommended DC Operating) | |
| VPP - Z(f) Spec Zmax, Freq: 20MHz (Recommended DC Operating) | |
| Internal read command to first data | |
| ACT to internal read or write delay time | |
| Row Precharge Time | |
| ACT to PRE command period | |
| ACT to ACT or REF command period | |
| CAS Write Latency | |
| tAAmin | |
| tCK(AVG) min | |
| tCK(AVG) max | |
| Read CL / Write CWL | |
| tRCDmin/tRPmin | |
| tCK(AVG) | |
| Default dimensional tolerance | |
| Module height (Front) | |
| Notch dimension reference | |
| PCB segment length | |
| Thickness reference | |
| Edge/contact dimension | |
| Back keep-out / corner radius | |
| Contact pin reference | |
| Side dimension (max) | |
| Pin pitch | |
| Contact bevel dimension (Detail of Contacts A, F) | |
| Contact pin reference (Detail of Contacts B) | |
| Contact pin reference (Detail of Contacts C) | |
| Contact bevel dimension (Detail of Contacts D) | |
| Non-metalized keep out area (Detail of Contacts B) | |
| Keep out area max dimension (Detail of Contacts B) | |
| Non-metalized keep out area (Detail of Contacts D) | |
| Detail F contact spacing | |
| Detail B/C/D reference dimension | |
| Bank configuration | |
| Bank groups | |
| Generation | |
| RON34Pd VOLdc=0.5*VDDQ Unit | |
| RON34Pd VOMdc=0.8*VDDQ Nom | |
| RON34Pd VOMdc=0.8*VDDQ Unit | |
| RON34Pd VOHdc=0.95*VDDQ Nom | |
| RON34Pd VOHdc=0.95*VDDQ Unit | |
| RON34Pu VOLdc=0.5*VDDQ Nom | |
| RON34Pu VOLdc=0.5*VDDQ Unit | |
| RON34Pu VOMdc=0.8*VDDQ Nom | |
| RON34Pu VOMdc=0.8*VDDQ Unit | |
| RON34Pu VOHdc=0.95*VDDQ Nom | |
| RON34Pu VOHdc=0.95*VDDQ Unit | |
| RON48Pd VOLdc=0.5*VDDQ Nom | |
| RON48Pd VOLdc=0.5*VDDQ Unit | |
| RON48Pd VOMdc=0.8*VDDQ Nom | |
| RON48Pd VOMdc=0.8*VDDQ Unit | |
| RON48Pd VOHdc=0.95*VDDQ Nom | |
| RON48Pd VOHdc=0.95*VDDQ Unit | |
| RON48Pu VOLdc=0.5*VDDQ Nom | |
| RON48Pu VOLdc=0.5*VDDQ Unit | |
| RON48Pu VOMdc=0.8*VDDQ Nom | |
| RON48Pu VOMdc=0.8*VDDQ Unit | |
| RON48Pu VOHdc=0.95*VDDQ Nom | |
| RON48Pu VOHdc=0.95*VDDQ Unit | |
| LB RON34Pd VOLdc=0.5*VDDQ Nom | |
| LB RON34Pd VOLdc=0.5*VDDQ Unit | |
| LB RON34Pd VOMdc=0.8*VDDQ Nom | |
| LB RON34Pd VOMdc=0.8*VDDQ Unit | |
| LB RON34Pd VOHdc=0.95*VDDQ Nom | |
| LB RON34Pd VOHdc=0.95*VDDQ Unit | |
| LB RON34Pu VOLdc=0.5*VDDQ Nom | |
| LB RON34Pu VOLdc=0.5*VDDQ Unit | |
| LB RON34Pu VOMdc=0.8*VDDQ Nom | |
| LB RON34Pu VOMdc=0.8*VDDQ Unit | |
| LB RON34Pu VOHdc=0.95*VDDQ Nom | |
| LB RON34Pu VOHdc=0.95*VDDQ Unit | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-3200 MIN | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-3200 MAX | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-3600 MIN | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-3600 MAX | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-4000 MIN | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-4000 MAX | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-4400 MIN | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-4400 MAX | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-4800 MIN | |
| Loopback LBDQS Output Low Time (tLBQSL) DDR5-4800 MAX | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-3200 MIN | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-3200 MAX | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-3600 MIN | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-3600 MAX | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-4000 MIN | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-4000 MAX | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-4400 MIN | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-4400 MAX | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-4800 MIN | |
| Loopback LBDQS Output High Time (tLBQSH) DDR5-4800 MAX | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3200 MIN | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3200 MAX | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3600 MIN | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3600 MAX | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4000 MIN | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4000 MAX | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4400 MIN | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4400 MAX | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4800 MIN | |
| Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4800 MAX | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3200 MIN | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3200 MAX | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3600 MIN | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3600 MAX | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4000 MIN | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4000 MAX | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4400 MIN | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4400 MAX | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4800 MIN | |
| Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4800 MAX | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3200 MIN | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3200 MAX | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3600 MIN | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3600 MAX | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4000 MIN | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4000 MAX | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4400 MIN | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4400 MAX | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4800 MIN | |
| Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4800 MAX | |
| Alert_n RONPd VOLdc=0.1*VDDQ Unit | |
| Alert_n RONPd VOMdc=0.8*VDDQ Unit | |
| Alert_n RONPd VOHdc=0.95*VDDQ Unit | |
| CT RONPd_CT VOBdc=0.2xVDDQ Max | |
| CT RONPd_CT VOLdc=0.5xVDDQ Max | |
| CT RONPd_CT VOMdc=0.8xVDDQ Max | |
| CT RONPd_CT VOHdc=0.95xVDDQ Max | |
| CT RONPu_CT VOBdc=0.2xVDDQ Max | |
| CT RONPu_CT VOLdc=0.5xVDDQ Max | |
| CT RONPu_CT VOMdc=0.8xVDDQ Max | |
| CT RONPu_CT VOHdc=0.95xVDDQ Max | |
| CT uncalibrated drive strength tolerance | |
| Single ended output slew rate SRQse DDR5-3200 MIN | |
| Single ended output slew rate SRQse DDR5-3200 MAX | |
| Single ended output slew rate SRQse DDR5-3600 MIN | |
| Single ended output slew rate SRQse DDR5-3600 MAX | |
| Single ended output slew rate SRQse DDR5-4000 MIN | |
| Single ended output slew rate SRQse DDR5-4000 MAX | |
| Single ended output slew rate SRQse DDR5-4400 MIN | |
| Single ended output slew rate SRQse DDR5-4400 MAX | |
| Single ended output slew rate SRQse DDR5-4800 MIN | |
| Single ended output slew rate SRQse DDR5-4800 MAX | |
| Differential output slew rate SRQdiff DDR5-3200 MIN | |
| Differential output slew rate SRQdiff DDR5-3200 MAX | |
| Differential output slew rate SRQdiff DDR5-3600 MIN | |
| Differential output slew rate SRQdiff DDR5-3600 MAX | |
| Differential output slew rate SRQdiff DDR5-4000 MIN | |
| Differential output slew rate SRQdiff DDR5-4000 MAX | |
| Differential output slew rate SRQdiff DDR5-4400 MIN | |
| Differential output slew rate SRQdiff DDR5-4400 MAX | |
| Differential output slew rate SRQdiff DDR5-4800 MIN | |
| Differential output slew rate SRQdiff DDR5-4800 MAX | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3200 MIN | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3200 MAX | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3200 MIN | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3200 MAX | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3200 MIN | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3200 MAX | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3200 MIN | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3200 MAX | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3600 MIN | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3600 MAX | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3600 MIN | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3600 MAX | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3600 MIN | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3600 MAX | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3600 MIN | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3600 MAX | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4000 MIN | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4000 MAX | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4000 MIN | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4000 MAX | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4000 MIN | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4000 MAX | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4000 MIN | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4000 MAX | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4400 MIN | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4400 MAX | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4400 MIN | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4400 MAX | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4400 MIN | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4400 MAX | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4400 MIN | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4400 MAX | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4800 MIN | |
| Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4800 MAX | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4800 MIN | |
| Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4800 MAX | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4800 MIN | |
| Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4800 MAX | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4800 MIN | |
| Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4800 MAX | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3200 MIN | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3200 MAX | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3200 MIN | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3200 MAX | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3200 MIN | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3200 MAX | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3200 MIN | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3200 MAX | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3200 MIN | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3200 MAX | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3600 MIN | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3600 MAX | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3600 MIN | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3600 MAX | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3600 MIN | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3600 MAX | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3600 MIN | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3600 MAX | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3600 MIN | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3600 MAX | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4000 MIN | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4000 MAX | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4000 MIN | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4000 MAX | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4000 MIN | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4000 MAX | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4000 MIN | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4000 MAX | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4000 MIN | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4000 MAX | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4400 MIN | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4400 MAX | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4400 MIN | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4400 MAX | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4400 MIN | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4400 MAX | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4400 MIN | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4400 MAX | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4400 MIN | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4400 MAX | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4800 MIN | |
| Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4800 MAX | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4800 MIN | |
| Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4800 MAX | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4800 MIN | |
| Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4800 MAX | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4800 MIN | |
| Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4800 MAX | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4800 MIN | |
| Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4800 MAX | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3200 MIN | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3200 MAX | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3600 MIN | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3600 MAX | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4000 MIN | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4000 MAX | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4400 MIN | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4400 MAX | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4800 MIN | |
| Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4800 MAX | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3200 MIN | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3200 MAX | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3600 MIN | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3600 MAX | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4000 MIN | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4000 MAX | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4400 MIN | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4400 MAX | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4800 MIN | |
| Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4800 MAX | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3200 MIN | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3200 MAX | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3600 MIN | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3600 MAX | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4000 MIN | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4000 MAX | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4400 MIN | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4400 MAX | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4800 MIN | |
| Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4800 MAX | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3200 MIN | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3200 MAX | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3600 MIN | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3600 MAX | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4000 MIN | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4000 MAX | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4400 MIN | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4400 MAX | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4800 MIN | |
| Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4800 MAX | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3200 MIN | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3200 MAX | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3600 MIN | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3600 MAX | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4000 MIN | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4000 MAX | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4400 MIN | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4400 MAX | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4800 MIN | |
| Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4800 MAX | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3200 MIN | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3200 MAX | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3600 MIN | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3600 MAX | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4000 MIN | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4000 MAX | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4400 MIN | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4400 MAX | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4800 MIN | |
| Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4800 MAX | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3200 MIN | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3200 MAX | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3600 MIN | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3600 MAX | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4000 MIN | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4000 MAX | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4400 MIN | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4400 MAX | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4800 MIN | |
| Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4800 MAX | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3200 MIN | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3200 MAX | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3600 MIN | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3600 MAX | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4000 MIN | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4000 MAX | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4400 MIN | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4400 MAX | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4800 MIN | |
| Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4800 MAX | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3200 MIN | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3200 MAX | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3600 MIN | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3600 MAX | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4000 MIN | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4000 MAX | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4400 MIN | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4400 MAX | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4800 MIN | |
| Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4800 MAX | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3200 MIN | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3200 MAX | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3600 MIN | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3600 MAX | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4000 MIN | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4000 MAX | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4400 MIN | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4400 MAX | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4800 MIN | |
| Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4800 MAX | |
| Internal read command to first data (tAA) | |
| ACT to internal read or write delay time (tRCD) | |
| Row Precharge Time (tRP) | |
| ACT to ACT or REF command period (tRC) | |
| Module IDD basis note | |
| Module length (inner/PCB) | |
| Edge to notch/feature offset | |
| Module height (full) | |
| Height to key/notch | |
| Dimension 3.35 | |
| Dimension 62.90 | |
| Dimension 57.80 | |
| Dimension 2.70 | |
| Notch center offset (Back) | |
| PCB thickness | |
| Dimension 14.10 | |
| Dimension 3.00 | |
| Dimension 8.00 | |
| Dimension 11.00 | |
| Pin 35 | |
| Pin 47 | |
| Pin 105 | |
| Pin 117 | |
| Component | |
| Contact height (Detail A/F) | |
| Contact thickness (Detail A/F) | |
| Dimension 5.95 | |
| Dimension 3.85 | |
| Dimension 4.30 | |
| Dimension 1.50 | |
| Dimension 0.2 | |
| Dimension 0.20 | |
| Contact bevel start (Detail B) | |
| Contact bevel end (Detail B) | |
| Contact span inner (Detail B) | |
| Contact span outer (Detail B) | |
| Pin 39 | |
| Pin 51 | |
| Contact bevel start (Detail C) | |
| Contact bevel end (Detail C) | |
| Contact span inner (Detail C) | |
| Contact span outer (Detail C) | |
| Pin 122 | |
| Pin 110 | |
| Dimension 2.10 (Detail D) | |
| Contact height (Detail D) | |
| Non-metalized keep out (Detail A/F) | |
| Keep out Max 0.30 (Detail A/F) | |
| Keep out Max 0.35 (Detail A/F) | |
| Keep out Max 0.25 (Detail A/F) | |
| Non-metalized keep out (Detail D) | |
| Keep out Max 0.30 (Detail D) | |
| Keep out Max 0.35 (Detail D) | |
| Keep out Max 0.30 (Detail D second) | |
| REFab Normal tREFI1 (0°C <= TCASE <= 85°C) | |
| REFab Normal tREFI1 (85°C < TCASE <= 95°C) | |
| REFab Fine Granularity tREFI2 (0°C <= TCASE <= 85°C) | |
| REFab Fine Granularity tREFI2 (85°C < TCASE <= 95°C) | |
| REFsb Fine Granularity tREFIsb (0°C <= TCASE <= 85°C) | |
| REFsb Fine Granularity tREFIsb (85°C < TCASE <= 95°C) | |
| VDD Device Supply Voltage Min | |
| VDD Device Supply Voltage Typ | |
| VDD Device Supply Voltage Max | |
| VDD Z(f) Spec 2MHz-10MHz Zmax | |
| VDDQ Supply Voltage for I/O Min | |
| VDDQ Supply Voltage for I/O Typ | |
| VDDQ Supply Voltage for I/O Max | |
| VDDQ Z(f) Spec 2MHz-10MHz Zmax | |
| VPP Core Power Voltage Min | |
| VPP Core Power Voltage Typ | |
| VPP Core Power Voltage Max | |
| VPP Z(f) Spec 2MHz-10MHz Zmax | |
| Rj RMS value of N-UI Jitter (N=2,3) (tCK_NUI_Rj_NoBUJ) Max | |
| Dj pp value of N-UI Jitter (N=2,3) (tCK_NUI_Dj_NoBUJ) Max | |
| Tj value of N-UI Jitter (N=2,3) (tCK_NUI_Tj_NoBUJ) Max | |
| Rj RMS value of N-UI Jitter (N=4..30) (tCK_NUI_Rj_NoBUJ) Max | |
| Dj pp value of N-UI Jitter (N=4..30) (tCK_NUI_Dj_NoBUJ) Max | |
| Tj value of N-UI Jitter (N=4..30) (tCK_NUI_Tj_NoBUJ) Max | |
| DRAM Reference clock frequency tCK Min | |
| DRAM Reference clock frequency tCK Max | |
| Clock differential input crosspoint voltage ratio VIX_CK_Ratio Max (DDR5-3200-4800) | |
| Clock differential input crosspoint voltage ratio VIX_CK_Ratio Max (DDR5-6800-8400) | |
| Input Clock Voltage Sensitivity (differential pp) VRx_CK Max | |
| VIHdiffCK Differential input high measurement level (CK_t, CK_c) (DDR5 3200-6400) | |
| VILdiffCK Differential input low measurement level (CK_t, CK_c) (DDR5 3200-6400) | |
| Delay of any data lane relative to the DQS_t/DQS_c crossing (tRx_DQS2DQ) Min | |
| Delay of any data lane relative to the DQS_t/DQS_c crossing (tRx_DQS2DQ) Max | |
| Applied DCD and Rj RMS to the DQS Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS Max | |
| DQS differential input crosspoint voltage ratio VIX_DQS_Ratio Max (DDR5-3200-4800) | |
| VIHdiffDQS Differential input high measurement level (DQS_t, DQS_c) (DDR5 3200-6400) | |
| VILdiffDQS Differential input low measurement level (DQS_t, DQS_c) (DDR5 3200-6400) | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) Max | |
| Minimum DQ Rx input voltage sensitivity applied around Vref VRx_DQ Max | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) Min | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) Min | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Injected voltage noise as PRBS23, or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min | |
| Injected voltage noise as PRBS23, or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics) Min | |
| Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics) Max | |
| tCT_IS Min | |
| tCT_Enable Min | |
| tCT_Valid Max | |
| TEN AC Input High Voltage VIH(AC)_TEN Min | |
| TEN AC Input High Voltage VIH(AC)_TEN Max | |
| TEN DC Input High Voltage VIH(DC)_TEN Min | |
| TEN DC Input High Voltage VIH(DC)_TEN Max | |
| TEN DC Input Low Voltage VIL(DC)_TEN Min | |
| TEN DC Input Low Voltage VIL(DC)_TEN Max | |
| TEN AC Input Low Voltage VIL(AC)_TEN Min | |
| TEN AC Input Low Voltage VIL(AC)_TEN Max | |
| TEN Input signal Falling time TF_input_TEN Max | |
| TEN Input signal Rising time TR_input_TEN Max | |
| VIH(AC)_RESET AC Input High Voltage Min | |
| VIH(AC)_RESET AC Input High Voltage Max | |
| VIH(DC)_RESET DC Input High Voltage Min | |
| VIH(DC)_RESET DC Input High Voltage Max | |
| VIL(DC)_RESET DC Input Low Voltage Min | |
| VIL(DC)_RESET DC Input Low Voltage Max | |
| VIL(AC)_RESET AC Input Low Voltage Min | |
| VIL(AC)_RESET AC Input Low Voltage Max | |
| TR_RESET Rising time Max | |
| tPW_RESET RESET pulse width Min | |
| 34Ω RON34Pd VOLdc= 0.5*VDDQ Min | |
| 34Ω RON34Pd VOLdc= 0.5*VDDQ Nom | |
| 34Ω RON34Pd VOLdc= 0.5*VDDQ Max | |
| 34Ω RON34Pd VOMdc= 0.8*VDDQ Min | |
| 34Ω RON34Pd VOMdc= 0.8*VDDQ Nom | |
| 34Ω RON34Pd VOMdc= 0.8*VDDQ Max | |
| 34Ω RON34Pd VOHdc= 0.95*VDDQ Min | |
| 34Ω RON34Pd VOHdc= 0.95*VDDQ Nom | |
| 34Ω RON34Pd VOHdc= 0.95*VDDQ Max | |
| 34Ω RON34Pu VOLdc= 0.5*VDDQ Min | |
| 34Ω RON34Pu VOLdc= 0.5*VDDQ Nom | |
| 34Ω RON34Pu VOLdc= 0.5*VDDQ Max | |
| 34Ω RON34Pu VOMdc= 0.8*VDDQ Min | |
| 34Ω RON34Pu VOMdc= 0.8*VDDQ Nom | |
| 34Ω RON34Pu VOMdc= 0.8*VDDQ Max | |
| 34Ω RON34Pu VOHdc= 0.95*VDDQ Min | |
| 34Ω RON34Pu VOHdc= 0.95*VDDQ Nom | |
| 34Ω RON34Pu VOHdc= 0.95*VDDQ Max | |
| 48Ω RON48Pd VOLdc= 0.5*VDDQ Min | |
| 48Ω RON48Pd VOLdc= 0.5*VDDQ Nom | |
| 48Ω RON48Pd VOLdc= 0.5*VDDQ Max | |
| 48Ω RON48Pd VOMdc= 0.8*VDDQ Min | |
| 48Ω RON48Pd VOMdc= 0.8*VDDQ Nom | |
| 48Ω RON48Pd VOMdc= 0.8*VDDQ Max | |
| 48Ω RON48Pd VOHdc= 0.95*VDDQ Min | |
| 48Ω RON48Pd VOHdc= 0.95*VDDQ Nom | |
| 48Ω RON48Pd VOHdc= 0.95*VDDQ Max | |
| 48Ω RON48Pu VOLdc= 0.5*VDDQ Min | |
| 48Ω RON48Pu VOLdc= 0.5*VDDQ Nom | |
| 48Ω RON48Pu VOLdc= 0.5*VDDQ Max | |
| 48Ω RON48Pu VOMdc= 0.8*VDDQ Min | |
| 48Ω RON48Pu VOMdc= 0.8*VDDQ Nom | |
| 48Ω RON48Pu VOMdc= 0.8*VDDQ Max | |
| 48Ω RON48Pu VOHdc= 0.95*VDDQ Min | |
| 48Ω RON48Pu VOHdc= 0.95*VDDQ Nom | |
| 48Ω RON48Pu VOHdc= 0.95*VDDQ Max | |
| Mismatch between pull-up and pull-down MMPuPd (VOMdc=0.8*VDDQ) Min | |
| Mismatch between pull-up and pull-down MMPuPd (VOMdc=0.8*VDDQ) Max | |
| Mismatch DQ-DQ within byte variation pull-up MMPudd (VOMdc=0.8*VDDQ) Max | |
| Mismatch DQ-DQ within byte variation pull-dn MMPddd (VOMdc=0.8*VDDQ) Max | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Min | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Nom | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Max | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Min | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Nom | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Max | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Min | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Nom | |
| Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Max | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Min | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Nom | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Max | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Min | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Nom | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Max | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Min | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Nom | |
| Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Max | |
| Loopback Mismatch between pull-up and pull-down MMPuPd Min | |
| Loopback Mismatch between pull-up and pull-down MMPuPd Max | |
| Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd Max | |
| Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd Max | |
| Loopback LBDQS Output Low Time tLBQSL Min | |
| Loopback LBDQS Output High Time tLBQSH Min | |
| Loopback LBDQS to LBDQ Skew tLBDQSQ Min | |
| Loopback LBDQ Output Time from LBDQS tLBQH Min | |
| Loopback Data valid window (tLBQH-tLBDQSQ) tLBDVW Min | |
| CT Mode 34Ω RONPd_CT VOBdc = 0.2 x VDDQ Max | |
| CT Mode 34Ω RONPd_CT VOLdc = 0.5 x VDDQ Max | |
| CT Mode 34Ω RONPd_CT VOMdc = 0.8 x VDDQ Max | |
| CT Mode 34Ω RONPd_CT VOHdc = 0.95 x VDDQ Max | |
| CT Mode 34Ω RONPu_CT VOBdc = 0.2 x VDDQ Max | |
| CT Mode 34Ω RONPu_CT VOLdc = 0.5 x VDDQ Max | |
| CT Mode 34Ω RONPu_CT VOMdc = 0.8 x VDDQ Max | |
| CT Mode 34Ω RONPu_CT VOHdc = 0.95 x VDDQ Max | |
| CT Mode uncalibrated drive strength tolerance | |
| VOH Output high measurement level (for output SR) (DDR5-3200-6400) | |
| VOL Output low measurement level (for output SR) (DDR5-3200-6400) | |
| VOH Output high measurement level for Loopback Signals (DDR5-3200-6400) | |
| VOL Output low measurement level for Loopback Signals (DDR5-3200-6400) | |
| Single ended output slew rate SRQse Min | |
| Single ended output slew rate SRQse Max | |
| VOHdiff Differential output high measurement level (for output SR) (DDR5-3200-6400) | |
| VOLdiff Differential output low measurement level (for output SR) (DDR5-3200-6400) | |
| Differential output slew rate SRQdiff Min | |
| Differential output slew rate SRQdiff Max | |
| Rj RMS Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Rj_NoBUJ Max | |
| Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ Max | |
| Rj RMS Value of N-UI jitter without BUJ (1<N<4) tTx_DQS_NUI_Rj_NoBUJ Max | |
| Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ Max | |
| Rj RMS of 1-UI jitter without BUJ tTx_DQ_1UI_Rj_NoBUJ Max | |
| Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ Max | |
| Rj RMS of N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Rj_NoBUJ Max | |
| Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ Max | |
| Delay of any data lane relative to strobe lane tTx_DQS2DQ Min | |
| Delay of any data lane relative to strobe lane tTx_DQS2DQ Max | |
| Eye Height at transmitter with DQ-DQS skew of 1UI TxEH_DQ_SES_1UI Min | |
| Eye Width at transmitter with DQ-DQS skew of 1UI TxEW_DQ_SES_1UI Min | |
| Eye Height at transmitter with DQ-DQS skew of 2UI TxEH_DQ_SES_2UI Min | |
| Eye Width at transmitter with DQ-DQS skew of 2UI TxEW_DQ_SES_2UI Min | |
| Eye Height at transmitter with DQ-DQS skew of 3UI TxEH_DQ_SES_3UI Min | |
| Eye Width at transmitter with DQ-DQS skew of 3UI TxEW_DQ_SES_3UI Min | |
| Eye Height at transmitter with DQ-DQS skew of 4UI TxEH_DQ_SES_4UI Min | |
| Eye Width at transmitter with DQ-DQS skew of 4UI TxEW_DQ_SES_4UI Min | |
| Eye Height at transmitter with DQ-DQS skew of 5UI TxEH_DQ_SES_5UI Min | |
| Eye Width at transmitter with DQ-DQS skew of 5UI TxEW_DQ_SES_5UI Min | |
| IDD measurement: '0'/'LOW' defined | |
| IDD measurement: '1'/'HIGH' defined | |
| IDD measurement: 'MID-LEVEL' defined | |
| IDD measurement: TCASE range | |
| IDDQ0F current definition | |
| IPP0F current definition | |
| IDDQ2N current definition | |
| IPP2N current definition | |
| IDDQ2NT (Optional) current definition | |
| IPP2NT (Optional) current definition | |
| IDDQ2P current definition | |
| IPP2P current definition | |
| IDDQ3N current definition | |
| IPP3N current definition | |
| IDDQ3P current definition | |
| IPP3P current definition | |
| IDDQ4R current definition | |
| IPP4R current definition | |
| IDDQ4W current definition | |
| IPP4W current definition | |
| IDDQ5B current definition | |
| IPP5B current definition | |
| IDDQ5F current definition | |
| IPP5F current definition | |
| IDDQ5C current definition | |
| IPP5C current definition | |
| IDDQ6N current definition | |
| IPP6N current definition | |
| IDDQ6E current definition | |
| IPP6E current definition | |
| IDDQ7 current definition | |
| IPP7 current definition | |
| IDDQ8 current definition | |
| IPP8 current definition | |
| IDDQ9 (Optional) current definition | |
| IPP9 (Optional) current definition | |
| IDD6N TCASE Normal Temperature Range | |
| IDD6E TCASE Extended Temperature Range | |
| IDD measurement Burst Length | |
| IDD measurement Pull-Up Output Driver Impedance Control | |
| IDD measurement Pull-Down Output Driver Impedance Control | |
| IDD measurement RTT_NOM_WR = RTT_NOM_RD | |
| IDD measurement RTT_WR | |
| Module type / configuration | |
| Module length (Back, outer) | |
| Module length (Back, inner) | |
| Notch/feature height | |
| Component clearance dimension | |
| Component height (Detail E reference) | |
| Detail E callout value | |
| Component height (left) | |
| Dimension (Front, left segment) | |
| Dimension (Front, right segment) | |
| Contact pitch / lead pitch | |
| Edge radius | |
| Dimension (Detail A) | |
| Detail B dimension | |
| Contact dimension (A, F) | |
| Contact dimension (E) | |
| Contact dimension (B) | |
| Pin number callout (Detail B) | |
| Contact dimension (C) | |
| Pin number callout (Detail C) | |
| Keep-out area note | |
| Keep-out area dimension | |
| Contact dimension (D) | |
| Keep-out area note (D) | |
| Keep-out area dimension (D) | |
| Address Table mapping | |
| Block diagram - module configuration | |
| Register output signals (A-side, 1Rank x4) | |
| Register output signals (B-side, 1Rank x4) | |
| Default resistor value (block diagram note) | |
| Data-bus signal assignment (A-side, 1Rank x4) | |
| DRAM block placement (A-side, 1Rank x4, page2) | |
| Data-bus resistor value (note) | |
| DRAM ZQ pin resistor (note) | |
| Block diagram - module configuration (alternate) | |
| Register output signals (A-side, 2Rank x8) | |
| Register output signals (B-side, 2Rank x8) | |
| Default resistor value (block diagram note, 2Rank x8) | |
| DRAM block placement (A-side, 2Rank x8, page2) | |
| Data-bus signal assignment (A-side, 2Rank x8) | |
| DRAM block placement (B-side, 2Rank x8, page2) | |
| Data-bus signal assignment (B-side, 2Rank x8) | |
| Data-bus resistor value (note, 2Rank x8) | |
| DRAM ZQ pin resistor (note, 2Rank x8) | |
| VIN, VOUT | |
| TSTG | |
| tREFI1 (REFab Normal) | |
| tREFI2 (REFab Fine Granularity) | |
| tREFIsb (REFsb Fine Granularity) | |
| VDD Device Supply Voltage | |
| VDD Z(f) Spec 2MHz to 10MHz | |
| VDD Z(f) Spec 20MHz | |
| VDDQ Supply Voltage for I/O | |
| VDDQ Z(f) Spec 2MHz to 10MHz | |
| VDDQ Z(f) Spec 20MHz | |
| VPP Core Power Voltage | |
| VPP Z(f) Spec 2MHz to 10MHz | |
| VPP Z(f) Spec 20MHz | |
| Rx Mask voltage - p-p (VciVW) | |
| Rx Timing Window (TcIVW) | |
| Input Slew Rate over VcIVW (SRIN_cIVW) | |
| Duty Cycle Error (tCK_Duty_UI_Error) | |
| Rj RMS value of N-UI Jitter, N=4..30 (tCK_NUI_Rj_NoBUJ) Max | |
| Dj pp value of N-UI Jitter, N=4..30 (tCK_NUI_Dj_NoBUJ) Max | |
| Tj value of N-UI Jitter, N=4..30 (tCK_NUI_Tj_NoBUJ) Max | |
| Input Clock Voltage Sensitivity differential pp (VRx_CK) Max | |
| Applicable family-level spec tables | |
| Output Driver Table 20 condition | |
| Loopback Output Driver Table 21 condition | |
| LB Mismatch pull-up/pull-down MMPuPd Min | |
| LB Mismatch pull-up/pull-down MMPuPd Max | |
| Loopback LBDQS Output Low Time MIN | |
| Loopback LBDQS Output Low Time MAX | |
| Loopback LBDQS Output High Time MIN | |
| Loopback LBDQS Output High Time MAX | |
| Loopback LBDQS to LBDQ Skew MIN | |
| Loopback LBDQS to LBDQ Skew MAX | |
| Loopback LBDQ Output Time from LBDQS MIN | |
| Loopback LBDQ Output Time from LBDQS MAX | |
| Loopback Data valid window per UI per DRAM MIN | |
| Loopback Data valid window per UI per DRAM MAX | |
| Table 22 note | |
| Alert RONPd Min @ VOLdc=0.1*VDDQ | |
| Alert RONPd Max @ VOLdc=0.1*VDDQ | |
| Alert RONPd Min @ VOMdc=0.8*VDDQ | |
| Alert RONPd Max @ VOMdc=0.8*VDDQ | |
| Alert RONPd Min @ VOHdc=0.95*VDDQ | |
| Alert RONPd Max @ VOHdc=0.95*VDDQ | |
| CT RONPd_CT Max @ VOBdc=0.2*VDDQ | |
| CT RONPd_CT Max @ VOLdc=0.5*VDDQ | |
| CT RONPd_CT Max @ VOMdc=0.8*VDDQ | |
| CT RONPd_CT Max @ VOHdc=0.95*VDDQ | |
| CT RONPu_CT Max @ VOBdc=0.2*VDDQ | |
| CT RONPu_CT Max @ VOLdc=0.5*VDDQ | |
| CT RONPu_CT Max @ VOMdc=0.8*VDDQ | |
| CT RONPu_CT Max @ VOHdc=0.95*VDDQ | |
| CT mode note | |
| VOH Output high measurement level (single-ended) | |
| VOL Output low measurement level (single-ended) | |
| VOH Output high measurement level (Loopback) | |
| VOL Output low measurement level (Loopback) | |
| Single ended output slew rate MIN | |
| Single ended output slew rate MAX | |
| VOHdiff Differential output high measurement level | |
| VOLdiff Differential output low measurement level | |
| Differential output slew rate MIN | |
| Differential output slew rate MAX | |
| Rj RMS 1-UI Jitter without BUJ MAX (tTx_DQS_1UI_Rj_NoBUJ) | |
| Dj pp 1-UI Jitter without BUJ MAX (tTx_DQS_1UI_Dj_NoBUJ) | |
| Rj RMS N-UI jitter without BUJ MAX (tTx_DQS_NUI_Rj_NoBUJ) | |
| Dj pp N-UI Jitter without BUJ MAX (tTx_DQS_NUI_Dj_NoBUJ) | |
| Tx DQS Jitter Rj max note | |
| Rj RMS 1-UI jitter without BUJ MAX (tTx_DQ_1UI_Rj_NoBUJ) | |
| Dj pp 1-UI jitter without BUJ MAX (tTx_DQ_1UI_Dj_NoBUJ) | |
| Rj RMS N-UI jitter without BUJ MAX (tTx_DQ_NUI_Rj_NoBUJ) | |
| Dj pp N-UI jitter without BUJ MAX (tTx_DQ_NUI_Dj_NoBUJ) | |
| Delay of any data lane relative to strobe lane MIN (tTx_DQS2DQ) | |
| Delay of any data lane relative to strobe lane MAX (tTx_DQS2DQ) | |
| Tx DQ Jitter Rj max note | |
| Eye Height @ DQ-DQS skew 1UI MIN (TxEH_DQ_SES_1UI) | |
| Eye Width @ DQ-DQS skew 1UI MIN (TxEW_DQ_SES_1UI) | |
| Eye Height @ DQ-DQS skew 2UI MIN (TxEH_DQ_SES_2UI) | |
| Eye Width @ DQ-DQS skew 2UI MIN (TxEW_DQ_SES_2UI) | |
| Eye Height @ DQ-DQS skew 3UI MIN (TxEH_DQ_SES_3UI) | |
| Eye Width @ DQ-DQS skew 3UI MIN (TxEW_DQ_SES_3UI) | |
| Eye Height @ DQ-DQS skew 4UI MIN (TxEH_DQ_SES_4UI) | |
| Eye Width @ DQ-DQS skew 4UI MIN (TxEW_DQ_SES_4UI) | |
| Eye Height @ DQ-DQS skew 5UI MIN (TxEH_DQ_SES_5UI) | |
| Eye Width @ DQ-DQS skew 5UI MIN (TxEW_DQ_SES_5UI) | |
| Module density | |
| Edge connector / PCB height | |
| Dimension to feature (left section) | |
| Dimension to feature (left section, inner) | |
| Tab/notch top dimension | |
| Top edge feature dimension | |
| Detail E dimension (lower) | |
| Notch radius | |
| Pin spacing / pitch | |
| Detail A dimension (lower) | |
| Detail A pin reference | |
| Front pin reference | |
| Back pin reference | |
| Component reference | |
| Detail of Contacts D keep out note | |
| Detail of Contacts D keep out dimension | |
| Keep out note (Detail B/C area) | |
| Keep out dimension | |
| Die base | |
| Training (VrefDQ / VrefCA / VrefCS) | |
| Maximum Power Saving Mode | |
| Multi-Purpose Command | |
| Per DRAM Addressability | |
| Connectivity Test | |
| Command mode support | |
| CRC | |
| Duty Cycle Adjuster (DCA) for Read - Global | |
| Per Pin DCA for Read | |
| Diagram title | |
| Resistor value (default) | |
| DRAM ZQ pin resistor | |
| Register block | |
| DRAM device byte labels (page1, top buffer row) | |
| DRAM device byte labels (page1, bottom buffer row) | |
| DRAM device routing labels (page2, top row A-side) | |
| DRAM device routing labels (page2, bottom row B-side) | |
| Module IDD note | |
| PCB length (overall) | |
| PCB length (between outer edges) | |
| Edge offset | |
| Segment dimension | |
| Height dimension (lower) | |
| Notch/feature dimension | |
| Component height | |
| Registering Clock Driver | |
| PCB thickness qualifier | |
| Contact key/notch dimension | |
| Contact width/position | |
| Contact pad length | |
| Contact pad width | |
| Contact pad dimension | |
| Non-metalized keep out area | |
| Detail reference | |
| Based on die | |
| ACT to PRE command period (max) | |
| tRCDmin / tRPmin | |
| Specification section | |
| Module current basis note | |
| General tolerance | |
| Module overall width (Front, outer) | |
| Module width (Front, inner) | |
| Edge/feature dimension | |
| Dimension (Front) | |
| Pad/feature spacing (Front) | |
| Non-metalized keep out area note | |
| Keep out area max dimension | |
| Block diagram central component | |
| Register input signals (A-side) | |
| Register output signals (A-side) | |
| Register output signals (B-side) | |
| DRAM components (A-channel row) | |
| DRAM components (B-channel row) | |
| Note (resistor tolerance) | |
| DRAM group A devices (page2) | |
| DRAM group B devices (page2) | |
| DRAM A-group data/strobe signals | |
| DRAM B-group data/strobe signals | |
| Note (DRAM DQ pin resistor) | |
| Rx Mask voltage - p-p (VciVW) - DDR5-3200 Max | |
| Rx Mask voltage - p-p (VciVW) - DDR5-3600 Max | |
| Rx Mask voltage - p-p (VciVW) - DDR5-4000 Max | |
| Rx Mask voltage - p-p (VciVW) - DDR5-4400 Max | |
| Rx Mask voltage - p-p (VciVW) - DDR5-4800 Max | |
| Rx Timing Window (TcIVW) - DDR5-3200 Max | |
| Rx Timing Window (TcIVW) - DDR5-3600 Max | |
| Rx Timing Window (TcIVW) - DDR5-4000 Max | |
| Rx Timing Window (TcIVW) - DDR5-4400 Max | |
| Rx Timing Window (TcIVW) - DDR5-4800 Max | |
| CA Input Pulse Amplitude (VIHL_AC) - DDR5-3200 | |
| CA Input Pulse Amplitude (VIHL_AC) - DDR5-3600 | |
| CA Input Pulse Amplitude (VIHL_AC) - DDR5-4000 | |
| CA Input Pulse Amplitude (VIHL_AC) - DDR5-4400 | |
| CA Input Pulse Amplitude (VIHL_AC) - DDR5-4800 | |
| CA Input Pulse Width (TcIPW) - DDR5-3200 | |
| CA Input Pulse Width (TcIPW) - DDR5-3600 | |
| CA Input Pulse Width (TcIPW) - DDR5-4000 | |
| CA Input Pulse Width (TcIPW) - DDR5-4400 | |
| CA Input Pulse Width (TcIPW) - DDR5-4800 | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3200 Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3200 Max | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3600 Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3600 Max | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4000 Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4000 Max | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4400 Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4400 Max | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4800 Min | |
| Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4800 Max | |
| DRAM Reference clock frequency (tCK) - DDR5-3200 Min | |
| DRAM Reference clock frequency (tCK) - DDR5-3200 Max | |
| DRAM Reference clock frequency (tCK) - DDR5-3600 Min | |
| DRAM Reference clock frequency (tCK) - DDR5-3600 Max | |
| DRAM Reference clock frequency (tCK) - DDR5-4000 Min | |
| DRAM Reference clock frequency (tCK) - DDR5-4000 Max | |
| DRAM Reference clock frequency (tCK) - DDR5-4400 Min | |
| DRAM Reference clock frequency (tCK) - DDR5-4400 Max | |
| DRAM Reference clock frequency (tCK) - DDR5-4800 Min | |
| DRAM Reference clock frequency (tCK) - DDR5-4800 Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-3200 Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-3600 Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-4000 Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-4400 Max | |
| Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-4800 Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-3200 Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-3600 Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-4000 Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-4400 Max | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-4800 Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-3200 Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-3600 Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-4000 Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-4400 Max | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-4800 Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-3200 Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-3600 Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-4000 Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-4400 Max | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-4800 Max | |
| Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-3200 Max | |
| Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-3600 Max | |
| Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-4000 Max | |
| Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-4400 Max | |
| Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-4800 Max | |
| Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-3200 Max | |
| Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-3600 Max | |
| Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-4000 Max | |
| Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-4400 Max | |
| Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-4800 Max | |
| Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-3200 Max | |
| Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-3600 Max | |
| Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-4000 Max | |
| Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-4400 Max | |
| Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-4800 Max | |
| Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-3200 Max | |
| Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-3600 Max | |
| Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-4000 Max | |
| Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-4400 Max | |
| Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-4800 Max | |
| Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-3200 Max | |
| Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-3600 Max | |
| Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-4000 Max | |
| Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-4400 Max | |
| Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-4800 Max | |
| Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-3200 Max | |
| Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-3600 Max | |
| Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-4000 Max | |
| Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-4400 Max | |
| Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-4800 Max | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - DDR5-3200-4800 Max | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - DDR5-6800-8400 Max | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-3200 Max | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-3600 Max | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-4000 Max | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-4400 Max | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-4800 Max | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3200 Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3200 Max | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3600 Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3600 Max | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4000 Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4000 Max | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4400 Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4400 Max | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4800 Min | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4800 Max | |
| DQ Timing Width (tRx_DQ_tMargin) - DDR5-3200 Min | |
| DQ Timing Width (tRx_DQ_tMargin) - DDR5-3600 Min | |
| DQ Timing Width (tRx_DQ_tMargin) - DDR5-4000 Min | |
| DQ Timing Width (tRx_DQ_tMargin) - DDR5-4400 Min | |
| DQ Timing Width (tRx_DQ_tMargin) - DDR5-4800 Min | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-3200 Max | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-3600 Max | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-4000 Max | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-4400 Max | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-4800 Max | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-3200 Max | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-3600 Max | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-4000 Max | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-4400 Max | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-4800 Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-3200 Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-3600 Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-4000 Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-4400 Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-4800 Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3200 Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3200 Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3600 Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3600 Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4000 Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4000 Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4400 Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4400 Max | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4800 Min | |
| Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4800 Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-3200 Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-3200 Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-3200 Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-3600 Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-3600 Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-3600 Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-4000 Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-4000 Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-4000 Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-4400 Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-4400 Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-4400 Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-4800 Max | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-4800 Max | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-4800 Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-3200 Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-3600 Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-4000 Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-4400 Max | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-4800 Max | |
| DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) - DDR5-3200-4800 Max | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3200 Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3200 Max | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3600 Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3600 Max | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4000 Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4000 Max | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4400 Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4400 Max | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4800 Min | |
| Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4800 Max | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-3200 Max | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-3600 Max | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-4000 Max | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-4400-6400 Max | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Min | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Min | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Min | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Min | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Min | |
| Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Min | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Min | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Min | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Min | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Min | |
| Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3200 Min | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3200 Max | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3600 Min | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3600 Max | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4000 Min | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4000 Max | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4400 Min | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4400 Max | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4800 Min | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4800 Max | |
| Output Driver DC Electrical Characteristics | |
| RON34Pd Unit @ VOLdc=0.5*VDDQ | |
| Mismatch between pull-up and pull-down MMPuPd Min @ VOMdc=0.8*VDDQ | |
| Mismatch between pull-up and pull-down MMPuPd Max @ VOMdc=0.8*VDDQ | |
| Mismatch DQ-DQ within byte variation pull-up MMPudd Max @ VOMdc=0.8*VDDQ | |
| Mismatch DQ-DQ within byte variation pull-dn MMPddd Max @ VOMdc=0.8*VDDQ | |
| Loopback Output Driver DC Electrical Characteristics | |
| LB Mismatch between pull-up and pull-down MMPuPd Min | |
| LB Mismatch between pull-up and pull-down MMPuPd Max | |
| LB Mismatch LBDQS-LBDQ within device variation pull-up MMPudd Max | |
| LB Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd Max | |
| Loopback driver Ron support | |
| tLBQSL Loopback LBDQS Output Low Time MIN | |
| tLBQSH Loopback LBDQS Output High Time MIN | |
| tLBDQSQ Loopback LBDQS to LBDQ Skew MIN | |
| tLBQH Loopback LBDQ Output Time from LBDQS MIN | |
| tLBDVW Loopback Data valid window MIN | |
| Loopback Output Timing note | |
| Alert RONPd Unit @ VOLdc=0.1*VDDQ | |
| Alert RONPd Unit @ VOHdc=0.95*VDDQ | |
| CT mode RONNOM | |
| CT mode drive strength tolerance | |
| Loopback VOH Output high measurement level (for output SR) | |
| Loopback VOL Output low measurement level (for output SR) | |
| Single-ended output levels note | |
| SRQse Single ended output slew rate MIN | |
| SRQse Single ended output slew rate MAX | |
| Single-ended output slew rate note | |
| Differential output levels note | |
| SRQdiff Differential output slew rate MIN | |
| SRQdiff Differential output slew rate MAX | |
| Differential output slew rate note | |
| tTx_DQS_1UI_Rj_NoBUJ Rj RMS Value of 1-UI Jitter without BUJ MAX | |
| tTx_DQS_1UI_Dj_NoBUJ Dj pp Value of 1-UI Jitter without BUJ MAX | |
| tTx_DQS_NUI_Rj_NoBUJ Rj RMS Value of N-UI jitter without BUJ (1<N<4) MAX | |
| tTx_DQS_NUI_Dj_NoBUJ Dj pp Value of N-UI Jitter without BUJ (1<N<4) MAX | |
| Tx DQS Jitter max Rj note | |
| tTx_DQ_1UI_Rj_NoBUJ Rj RMS of 1-UI jitter without BUJ MAX | |
| tTx_DQ_1UI_Dj_NoBUJ Dj pp 1-UI jitter without BUJ MAX | |
| tTx_DQ_NUI_Rj_NoBUJ Rj RMS of N-UI jitter without BUJ (1<N<4) MAX | |
| tTx_DQ_NUI_Dj_NoBUJ Dj pp N-UI jitter without BUJ (1<N<4) MAX | |
| tTx_DQS2DQ Delay of any data lane relative to strobe lane MIN | |
| tTx_DQS2DQ Delay of any data lane relative to strobe lane MAX | |
| Tx DQ Jitter max Rj note | |
| TxEH_DQ_SES_1UI Eye Height (skew DQ/DQS 1UI) MIN | |
| TxEW_DQ_SES_1UI Eye Width (skew DQ/DQS 1UI) MIN | |
| TxEH_DQ_SES_2UI Eye Height (skew DQ/DQS 2UI) MIN | |
| TxEW_DQ_SES_2UI Eye Width (skew DQ/DQS 2UI) MIN | |
| TxEH_DQ_SES_3UI Eye Height (skew DQ/DQS 3UI) MIN | |
| TxEW_DQ_SES_3UI Eye Width (skew DQ/DQS 3UI) MIN | |
| TxEH_DQ_SES_4UI Eye Height (skew DQ/DQS 4UI) MIN | |
| TxEW_DQ_SES_4UI Eye Width (skew DQ/DQS 4UI) MIN | |
| TxEH_DQ_SES_5UI Eye Height (skew DQ/DQS 5UI) MIN | |
| TxEW_DQ_SES_5UI Eye Width (skew DQ/DQS 5UI) MIN | |
| Tx DQ Stressed Eye BER note | |
| Default tolerance on all dimensions unless otherwise stated | |
| Front length (inner / PCB) | |
| Height (Front, top edge dimension) | |
| Dimension with tolerance (left vertical, Front) | |
| Notch / segment dimension (Front, lower) | |
| Dimension with tolerance (Front, right) | |
| Side thickness (PCB) | |
| Edge contact pitch | |
| Corner radius (max) | |
| Detail A height (top, Detail E reference) | |
| Contact pad height (Contacts A, F) | |
| Contact pad width (Contacts A, F) | |
| Contact pad width with tolerance (Contacts A, F) | |
| Contact gap / clearance (Contacts A, F) | |
| Dimension (Contacts E detail) | |
| Dimension with tolerance (Contacts E detail) | |
| Pin callout (Contacts B detail) | |
| Dimension (Contacts B detail) | |
| Pin callout (Contacts C detail) | |
| Dimension (Contacts C detail) | |
| Contact pad width (Contacts D detail) | |
| Contact pad width with tolerance (Contacts D detail) | |
| Non-metalized keep out area note (Contacts A,F) | |
| Keep out area max (Contacts A,F) | |
| Non-metalized keep out area note (Contacts D) | |
| Keep out area max (Contacts D) | |
| Dimension with tolerance (Detail F) | |
| Dimension (Detail F) | |
| Revision / date | |
| Module title | |
| Module length (overall, Front) | |
| Module length (Front) | |
| Module height dimension | |
| Vertical dimension | |
| Pitch dimension | |
| Detail E callout | |
| Corner radius (Detail A) | |
| Detail F callout | |
| Detail of Contacts B pin | |
| Detail of Contacts C pin | |
| Detail of Contacts D non-metalized keep out | |
| Detail of Contacts D max dimension | |
| Detail of Contacts (non-metalized keep out) | |
| Non-metalized keep out max dimension | |
| Application | |
| Block diagram title (page 1) | |
| Register output - Side A command/address | |
| Register output - Side A chip select 0 | |
| Register output - Side A clock (A copy) | |
| Register output - Side A clock (C copy) | |
| Register output - Side A chip select 0 (B copy) | |
| Register output - Side A reset | |
| Register output - Side A DERROR_IN | |
| Register output - Side A DLBD | |
| Register output - Side A DLBS | |
| Register output - Side B command/address | |
| Register output - Side B chip select 0 | |
| Register output - Side B clock (A copy) | |
| Register output - Side B clock (C copy) | |
| Register output - Side B chip select 0 (B copy) | |
| Register output - Side B reset | |
| Register output - Side B DERROR_IN | |
| Register output - Side B DLBD | |
| Register output - Side B DLBS | |
| Register input - DCA | |
| Register input - DCS | |
| Register input - DPAR | |
| Register input - DCK | |
| Register input - DRST | |
| Register input - ALERT_n | |
| DRAM device placement (front row, page 1) | |
| DRAM device placement (back row, page 1) | |
| Note 1 (page 1) | |
| Block diagram title (page 2) | |
| DRAM A-side command/address routing devices | |
| DRAM B-side command/address routing devices | |
| DQS/DQ net labels (A side, sample) | |
| Note 1 (page 2) | |
| Note 2 (page 2) | |
| VDD - Voltage on VDD pin relative to Vss (Absolute Maximum Rating) | |
| VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Maximum Rating) | |
| VPP - Voltage on VPP pin relative to Vss (Absolute Maximum Rating) | |
| VIN, VOUT - Voltage on any pin relative to Vss (Absolute Maximum Rating) | |
| TSTG - Storage Temperature (Absolute Maximum Rating) | |
| VDD - Z(f) Spec (Freq: 2MHz to 10MHz), Zmax | |
| VDD - Z(f) Spec (Freq: 20MHz), Zmax | |
| VDDQ - Z(f) Spec (Freq: 2MHz to 10MHz), Zmax | |
| VDDQ - Z(f) Spec (Freq: 20MHz), Zmax | |
| VPP - Z(f) Spec (Freq: 2MHz to 10MHz), Zmax | |
| VPP - Z(f) Spec (Freq: 20MHz), Zmax | |
| Module length (overall) | |
| Module length (PCB) | |
| Top edge to feature height | |
| Contact/feature dimension | |
| Front segment dimension (left) | |
| Front segment dimension (right) | |
| Feature/notch height dimension | |
| Notch/key offset | |
| Key position dimension | |
| Corner radius (typ) | |
| Internal radius | |
| Contact A/F detail dimension | |
| Contact E detail dimension | |
| Contact B detail dimension | |
| Contact C detail dimension | |
| Contact C keep-out | |
| Contact C keep-out max | |
| Contact D detail dimension | |
| Contact D keep-out | |
| Contact D keep-out max | |
| Feature dimension | |
| Bank count (x4/x8) | |
| Bank Groups (x4/x8/x16) | |
| Module description (diagram title) | |
| Register output A - command/address | |
| Register output A - chip select 0 | |
| Register output A - A-side clock | |
| Register output A - C-side clock | |
| Register output A - B chip select 0 | |
| Register output A - reset | |
| Register output A - data error in | |
| Register output A - loopback data | |
| Register output A - loopback strobe | |
| Register output B - command/address | |
| Register output B - chip select 0 | |
| Register output B - A-side clock | |
| Register output B - C-side clock | |
| Register output B - B chip select 0 | |
| Register output B - reset | |
| Register output B - data error in | |
| Register output B - loopback data | |
| Register output B - loopback strobe | |
| DRAM placement - front row A side | |
| DRAM placement - front row B side | |
| DRAM placement - back row A side | |
| DRAM placement - back row B side | |
| Note 1 (page 16) - resistor value | |
| DRAM device (A side, byte 0) | |
| Byte lane 0 strobe/data (A side) | |
| Byte lane 5 strobe/data (A side) | |
| DRAM device (A side, byte 1) | |
| Byte lane 1 strobe/data (A side) | |
| Byte lane 6 strobe/data (A side) | |
| DRAM device (A side, byte 2) | |
| Byte lane 2 strobe/data (A side) | |
| Byte lane 7 strobe/data (A side) | |
| DRAM device (A side, byte 3) | |
| Byte lane 3 strobe/data (A side) | |
| Byte lane 8 strobe/data (A side) | |
| DRAM device (A side, ECC byte) | |
| Check-bit lane 4 strobe/data (A side) | |
| Check-bit lane 9 strobe/data (A side) | |
| A-side command/address bus to devices | |
| DRAM device (B side, ECC byte) | |
| Check-bit lane 4 strobe/data (B side) | |
| Check-bit lane 9 strobe/data (B side) | |
| DRAM device (B side, byte 5) | |
| Byte lane 5 strobe/data (B side) | |
| Byte lane 0 strobe/data (B side) | |
| DRAM device (B side, byte 6) | |
| Byte lane 6 strobe/data (B side) | |
| Byte lane 1 strobe/data (B side) | |
| DRAM device (B side, byte 7) | |
| Byte lane 7 strobe/data (B side) | |
| Byte lane 2 strobe/data (B side) | |
| DRAM device (B side, byte 8) | |
| Byte lane 8 strobe/data (B side) | |
| Byte lane 3 strobe/data (B side) | |
| B-side command/address bus to devices | |
| Note 1 (page 17) - resistor value | |
| Note 2 (page 17) - ZQ resistor | |
| TEN AC Input High Voltage VIH(AC)_TEN (Min) | |
| TEN AC Input High Voltage VIH(AC)_TEN (Max) | |
| TEN DC Input High Voltage VIH(DC)_TEN (Min) | |
| TEN DC Input High Voltage VIH(DC)_TEN (Max) | |
| TEN DC Input Low Voltage VIL(DC)_TEN (Min) | |
| TEN DC Input Low Voltage VIL(DC)_TEN (Max) | |
| TEN AC Input Low Voltage VIL(AC)_TEN (Min) | |
| TEN AC Input Low Voltage VIL(AC)_TEN (Max) | |
| TEN Input signal Falling time TF_input_TEN (Max) | |
| TEN Input signal Rising time TR_input_TEN (Max) | |
| RESET_n AC Input High Voltage VIH(AC)_RESET (Min) | |
| RESET_n AC Input High Voltage VIH(AC)_RESET (Max) | |
| RESET_n DC Input High Voltage VIH(DC)_RESET (Min) | |
| RESET_n DC Input High Voltage VIH(DC)_RESET (Max) | |
| RESET_n DC Input Low Voltage VIL(DC)_RESET (Min) | |
| RESET_n DC Input Low Voltage VIL(DC)_RESET (Max) | |
| RESET_n AC Input Low Voltage VIL(AC)_RESET (Min) | |
| RESET_n AC Input Low Voltage VIL(AC)_RESET (Max) | |
| RESET_n Rising time TR_RESET (Max) | |
| RESET pulse width tPW_RESET (Min) | |
| RON34Pd VOLdc=0.5*VDDQ (Min) | |
| RON34Pd VOLdc=0.5*VDDQ (Nom) | |
| RON34Pd VOLdc=0.5*VDDQ (Max) | |
| RON34Pd VOMdc=0.8*VDDQ (Min) | |
| RON34Pd VOMdc=0.8*VDDQ (Nom) | |
| RON34Pd VOMdc=0.8*VDDQ (Max) | |
| RON34Pd VOHdc=0.95*VDDQ (Min) | |
| RON34Pd VOHdc=0.95*VDDQ (Nom) | |
| RON34Pd VOHdc=0.95*VDDQ (Max) | |
| RON34Pu VOLdc=0.5*VDDQ (Min) | |
| RON34Pu VOLdc=0.5*VDDQ (Nom) | |
| RON34Pu VOLdc=0.5*VDDQ (Max) | |
| RON34Pu VOMdc=0.8*VDDQ (Min) | |
| RON34Pu VOMdc=0.8*VDDQ (Nom) | |
| RON34Pu VOMdc=0.8*VDDQ (Max) | |
| RON34Pu VOHdc=0.95*VDDQ (Min) | |
| RON34Pu VOHdc=0.95*VDDQ (Nom) | |
| RON34Pu VOHdc=0.95*VDDQ (Max) | |
| RON48Pd VOLdc=0.5*VDDQ (Min) | |
| RON48Pd VOLdc=0.5*VDDQ (Nom) | |
| RON48Pd VOLdc=0.5*VDDQ (Max) | |
| RON48Pd VOMdc=0.8*VDDQ (Min) | |
| RON48Pd VOMdc=0.8*VDDQ (Nom) | |
| RON48Pd VOMdc=0.8*VDDQ (Max) | |
| RON48Pd VOHdc=0.95*VDDQ (Min) | |
| RON48Pd VOHdc=0.95*VDDQ (Nom) | |
| RON48Pd VOHdc=0.95*VDDQ (Max) | |
| RON48Pu VOLdc=0.5*VDDQ (Min) | |
| RON48Pu VOLdc=0.5*VDDQ (Nom) | |
| RON48Pu VOLdc=0.5*VDDQ (Max) | |
| RON48Pu VOMdc=0.8*VDDQ (Min) | |
| RON48Pu VOMdc=0.8*VDDQ (Nom) | |
| RON48Pu VOMdc=0.8*VDDQ (Max) | |
| RON48Pu VOHdc=0.95*VDDQ (Min) | |
| RON48Pu VOHdc=0.95*VDDQ (Nom) | |
| RON48Pu VOHdc=0.95*VDDQ (Max) | |
| Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ (Min) | |
| Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ (Max) | |
| Mismatch DQ-DQ within byte variation pull-up MMPudd, VOMdc=0.8*VDDQ (Max) | |
| Mismatch DQ-DQ within byte variation pull-dn MMPddd, VOMdc=0.8*VDDQ (Max) | |
| Loopback RON34Pd VOLdc=0.5*VDDQ (Min) | |
| Loopback RON34Pd VOLdc=0.5*VDDQ (Nom) | |
| Loopback RON34Pd VOLdc=0.5*VDDQ (Max) | |
| Loopback RON34Pd VOMdc=0.8*VDDQ (Min) | |
| Loopback RON34Pd VOMdc=0.8*VDDQ (Nom) | |
| Loopback RON34Pd VOMdc=0.8*VDDQ (Max) | |
| Loopback RON34Pd VOHdc=0.95*VDDQ (Min) | |
| Loopback RON34Pd VOHdc=0.95*VDDQ (Nom) | |
| Loopback RON34Pd VOHdc=0.95*VDDQ (Max) | |
| Loopback RON34Pu VOLdc=0.5*VDDQ (Min) | |
| Loopback RON34Pu VOLdc=0.5*VDDQ (Nom) | |
| Loopback RON34Pu VOLdc=0.5*VDDQ (Max) | |
| Loopback RON34Pu VOMdc=0.8*VDDQ (Min) | |
| Loopback RON34Pu VOMdc=0.8*VDDQ (Nom) | |
| Loopback RON34Pu VOMdc=0.8*VDDQ (Max) | |
| Loopback RON34Pu VOHdc=0.95*VDDQ (Min) | |
| Loopback RON34Pu VOHdc=0.95*VDDQ (Nom) | |
| Loopback RON34Pu VOHdc=0.95*VDDQ (Max) | |
| Loopback Mismatch between pull-up and pull-down MMPuPd (Min) | |
| Loopback Mismatch between pull-up and pull-down MMPuPd (Max) | |
| Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd (Max) | |
| Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd (Max) | |
| Loopback LBDQS Output Low Time tLBQSL (Min) DDR5-3200 | |
| Loopback LBDQS Output High Time tLBQSH (Min) DDR5-3200 | |
| Loopback LBDQS to LBDQ Skew tLBDQSQ (Min) DDR5-3200 | |
| Loopback LBDQ Output Time from LBDQS tLBQH (Min) DDR5-3200 | |
| Loopback Data valid window (tLBQH-tLBDQSQ) tLBDVW (Min) DDR5-3200 | |
| Alert_n RONPd VOLdc=0.1*VDDQ (Min) | |
| Alert_n RONPd VOLdc=0.1*VDDQ (Max) | |
| Alert_n RONPd VOMdc=0.8*VDDQ (Min) | |
| Alert_n RONPd VOMdc=0.8*VDDQ (Max) | |
| Alert_n RONPd VOHdc=0.95*VDDQ (Min) | |
| Alert_n RONPd VOHdc=0.95*VDDQ (Max) | |
| CT Mode RONPu_CT VOBdc=0.2xVDDQ (Max) | |
| CT Mode RONPu_CT VOLdc=0.5xVDDQ (Max) | |
| CT Mode RONPu_CT VOMdc=0.8xVDDQ (Max) | |
| CT Mode RONPu_CT VOHdc=0.95xVDDQ (Max) | |
| Single ended output slew rate SRQse (Min) DDR5-3200 | |
| Single ended output slew rate SRQse (Max) DDR5-3200 | |
| Differential output slew rate SRQdiff (Min) DDR5-3200 | |
| Differential output slew rate SRQdiff (Max) DDR5-3200 | |
| Rj RMS Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Rj_NoBUJ (Max) | |
| Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ (Max) | |
| Rj RMS Value of N-UI jitter without BUJ (1<N<4) tTx_DQS_NUI_Rj_NoBUJ (Max) | |
| Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ (Max) | |
| Rj RMS of 1-UI jitter without BUJ tTx_DQ_1UI_Rj_NoBUJ (Max) | |
| Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ (Max) | |
| Rj RMS of N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Rj_NoBUJ (Max) | |
| Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ (Max) | |
| Delay of any data lane relative to strobe lane tTx_DQS2DQ (Min) | |
| Delay of any data lane relative to strobe lane tTx_DQS2DQ (Max) | |
| Eye Height at transmitter, DQ/DQS skew 1UI TxEH_DQ_SES_1UI (Min) | |
| Eye Width at transmitter, DQ/DQS skew 1UI TxEW_DQ_SES_1UI (Min) | |
| Eye Height at transmitter, DQ/DQS skew 2UI TxEH_DQ_SES_2UI (Min) | |
| Eye Width at transmitter, DQ/DQS skew 2UI TxEW_DQ_SES_2UI (Min) | |
| Eye Height at transmitter, DQ/DQS skew 3UI TxEH_DQ_SES_3UI (Min) | |
| Eye Width at transmitter, DQ/DQS skew 3UI TxEW_DQ_SES_3UI (Min) | |
| Eye Height at transmitter, DQ/DQS skew 4UI TxEH_DQ_SES_4UI (Min) | |
| Eye Width at transmitter, DQ/DQS skew 4UI TxEW_DQ_SES_4UI (Min) | |
| Eye Height at transmitter, DQ/DQS skew 5UI TxEH_DQ_SES_5UI (Min) | |
| Eye Width at transmitter, DQ/DQS skew 5UI TxEW_DQ_SES_5UI (Min) | |
| Module length (inner, Front) | |
| Module height (Front, left) | |
| Module height (Front, right) | |
| Dimension (Front, right - inner) | |
| Edge/notch dimension (Front, lower-left) | |
| Key/notch position dimension (Front, lower) | |
| Key/notch dimension (Front, lower) | |
| Dimension (Front, lower-left detail) | |
| Dimension (Detail A area) | |
| Contact detail dimension (Contacts A, F) | |
| Contact detail dimension (Contacts E) | |
| Contact detail dimension (Contacts B) | |
| Pin number callout (Contacts B) | |
| Contact detail dimension (Contacts C) | |
| Pin number callout (Contacts C) | |
| Keep-out area note (Contacts C) | |
| Keep-out dimension (Contacts C) | |
| Contact detail dimension (Contacts D) | |
| Keep-out area note (Contacts D) | |
| Keep-out dimension (Contacts D) | |
| tREFI1 REFab Normal, 0C<=TCASE<=85C (rREFI) | |
| tREFI1 REFab Normal, 85C<TCASE<=95C (rREFI/2) | |
| tREFI2 REFab Fine Granularity, 0C<=TCASE<=85C (rREFI/2) | |
| tREFI2 REFab Fine Granularity, 85C<TCASE<=95C (rREFI/4) | |
| tREFIsb REFsb Fine Granularity, 0C<=TCASE<=85C (rREFI/(2*n)) | |
| tREFIsb REFsb Fine Granularity, 85C<TCASE<=95C (rREFI/(4*n)) | |
| VDD must be within 66mV of VDDQ | |
| DRAM Reference clock frequency tCK - Min (all grades) | |
| DRAM Reference clock frequency tCK - Max (all grades) | |
| Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) | |
| Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) | |
| Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) | |
| Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ) | |
| Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ) | |
| Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ) | |
| Rj RMS value of N-UI Jitter, where N=4,5,6,...,30 (tCK_NUI_Rj_NoBUJ) | |
| Dj pp value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Dj_NoBUJ) | |
| Tj value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Tj_NoBUJ) | |
| Tj definition for BER 1E-16 | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) | |
| Input Clock Voltage Sensitivity (differential pp) (VRx_CK) | |
| Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) | |
| DQ Timing Width (tRx_DQ_tMargin) | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) | |
| Delay of any data lane relative to the DQS_t/DQS_c crossing (tRx_DQS2DQ) | |
| Applied DCD to the DQS (tRx_DQS_DCD) | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) | |
| Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) | |
| DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) | |
| DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) | |
| Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) | |
| Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) | |
| Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye_Golden_Ref_Channel_1) | |
| Injected Random wide band (10 MHz-1 GHz) Jitter (Rj_Stressed_Eye_Golden_Ref_Channel_1) | |
| Injected voltage noise as PRBS23 or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) | |
| Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics) | |
| DFE tap range limit (|Tap-2| + |Tap-3| + |Tap-4|) | |
| Minimum BER requirement (Rx Stressed Eye) | |
| tCT_IS Connectivity Test - Min | |
| tCT_IS Connectivity Test - Max | |
| tCT_Enable Connectivity Test - Min | |
| tCT_Enable Connectivity Test - Max | |
| tCT_Valid Connectivity Test - Min | |
| tCT_Valid Connectivity Test - Max | |
| TEN AC Input High Voltage (VIH(AC)_TEN) | |
| TEN DC Input High Voltage (VIH(DC)_TEN) | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) | |
| TEN Input signal Falling time (TF_input_TEN) | |
| TEN Input signal Rising time (TR_input_TEN) | |
| AC Input High Voltage (VIH(AC)_RESET) | |
| DC Input High Voltage (VIH(DC)_RESET) | |
| DC Input Low Voltage (VIL(DC)_RESET) | |
| AC Input Low Voltage (VIL(AC)_RESET) | |
| Rising time (TR_RESET) | |
| RESET pulse width (tPW_RESET) | |
| IDD0 (Module Current) | |
| IDD0F (Module Current) | |
| IDD2N (Module Current) | |
| IDD2P (Module Current) | |
| IDD3N (Module Current) | |
| IDD3P (Module Current) | |
| IDD4R (Module Current) | |
| IDD4W (Module Current) | |
| IDD5 (Module Current) | |
| IDD5B (Module Current) | |
| IDD5C (Module Current) | |
| IDD6N (Module Current) | |
| IDD7 (Module Current) | |
| IDD8 (Module Current) | |
| Module current note | |
| Pad/notch offset dimension | |
| Pad/notch dimension | |
| Lower height dimension | |
| Detail E dimension (left) | |
| Detail E dimension (right) | |
| Detail A corner radius | |
| Contacts A,F height | |
| Contacts D non-metallized keep out area | |
| Contacts B/C non-metallized keep out area | |
| Register input clock true | |
| Register input clock complement | |
| Register input reset | |
| Register input loopback data | |
| Register input loopback strobe | |
| Register input alert | |
| Register output A - command/address bus | |
| Register output A - clock | |
| Register output B - command/address bus | |
| Register output B - clock | |
| DRAM count / layout | |
| DRAM byte mapping - row A (page2) | |
| DRAM byte mapping - row B (page2) | |
| Resistor value note (page2) | |
| VDD - Voltage on VDD pin relative to Vss (Absolute Max) | |
| VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Max) | |
| VPP - Voltage on VPP pin relative to Vss (Absolute Max) | |
| VIN, VOUT - Voltage on any pin relative to Vss (Absolute Max) | |
| TSTG - Storage Temperature (Absolute Max) | |
| tREFI1 REFab Normal (0°C <= TCASE <= 85°C) | |
| tREFI1 REFab Normal (85°C < TCASE <= 95°C) | |
| tREFI2 REFab Fine Granularity (0°C <= TCASE <= 85°C) | |
| tREFI2 REFab Fine Granularity (85°C < TCASE <= 95°C) | |
| tREFIsb REFsb Fine Granularity (0°C <= TCASE <= 85°C) | |
| tREFIsb REFsb Fine Granularity (85°C < TCASE <= 95°C) | |
| VDD Device Supply Voltage - Min (Low Freq Voltage Spec) | |
| Input Clock Jitter Specification applicability | |
| Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Min | |
| Input Clock Voltage Sensitivity differential pp (VRx_CK) Min | |
| Differential input high measurement level CK_t, CK_c (VIHdiffCK) | |
| Differential input low measurement level CK_t, CK_c (VILdiffCK) | |
| DQ Timing Width (tRx_DQ_tMargin) Max | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) Min | |
| Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) Max | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) Min | |
| Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) Max | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) Min | |
| Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) Max | |
| Applied DCD to the DQS (tRx_DQS_DCD) Min | |
| Applied Rj RMS to the DQS (tRx_DQS_Rj) Min | |
| DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Min | |
| DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max | |
| DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) Min | |
| Differential input high measurement level DQS_t, DQS_c (VIHdiffDQS) | |
| Differential input low measurement level DQS_t, DQS_c (VILdiffDQS) | |
| Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Min | |
| Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min | |
| Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) Min | |
| Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) Max | |
| CT Mode tCT_IS Min | |
| CT Mode tCT_IS Max | |
| CT Mode tCT_Enable Min | |
| CT Mode tCT_Enable Max | |
| CT Mode tCT_Valid Min | |
| CT Mode tCT_Valid Max | |
| TEN AC Input High Voltage (VIH(AC)_TEN) Max | |
| TEN DC Input High Voltage (VIH(DC)_TEN) Max | |
| TEN DC Input Low Voltage (VIL(DC)_TEN) Min | |
| TEN AC Input Low Voltage (VIL(AC)_TEN) Min | |
| TEN Input signal Falling time (TF_input_TEN) Min | |
| TEN Input signal Rising time (TR_input_TEN) Min | |
| RESET_n AC Input High Voltage (VIH(AC)_RESET) Max | |
| RESET_n DC Input High Voltage (VIH(DC)_RESET) Max | |
| RESET_n DC Input Low Voltage (VIL(DC)_RESET) Min | |
| RESET_n AC Input Low Voltage (VIL(AC)_RESET) Min | |
| RESET_n Rising time (TR_RESET) Min | |
| RESET pulse width (tPW_RESET) Max | |
| RZQ assumption | |
| RON34Pd Min | |
| RON34Pd Nom | |
| RON34Pd Max | |
| RON34Pu Min | |
| RON34Pu Nom | |
| RON34Pu Max | |
| RON48Pd Min | |
| RON48Pd Nom | |
| RON48Pd Max | |
| RON48Pu Min | |
| RON48Pu Nom | |
| RON48Pu Max | |
| Loopback RON34Pd Min | |
| Loopback RON34Pd Nom | |
| Loopback RON34Pd Max | |
| Loopback RON34Pu Min | |
| Loopback RON34Pu Nom | |
| Loopback RON34Pu Max | |
| Loopback MMPuPd Min | |
| Loopback MMPuPd Max | |
| Loopback MMPudd Max | |
| Loopback MMPddd Max | |
| Alert RONPd Min | |
| Alert RONPd Max | |
| CT RONPd_CT Max | |
| CT RONPu_CT Max | |
| VOH Loopback Output high measurement level (for output SR) | |
| VOL Loopback Output low measurement level (for output SR) | |
| Units of measure | |
| Default tolerance | |
| Edge inset / chamfer dimension | |
| Component height dimension | |
| Top notch / detail dimension | |
| Contact field width (left of key) | |
| Contact field width (right of key) | |
| Edge / board thickness dimension | |
| Key (notch) location dimension | |
| Contact pin number callout | |
| Contact length / height | |
| Contact gold-plating / max dimension | |
| Edge max dimension | |
| Annotation | |
| Contact field width | |
| Key/notch outer width | |
| Contact height | |
| Notch / clearance dimension | |
| Key/notch inner width | |
| Key/notch overall width | |
| Board / side thickness (max) | |
| Document title | |
| Product description | |
| Bank count (x16) | |
| block_diagram_title | |
| register_component | |
| register_input_signals_DCA | |
| register_input_signals_DCS | |
| register_input_signals_DPAR | |
| register_output_A_side_QACA | |
| register_output_B_side_QACA | |
| resistor_value_note | |
| dram_placement_rows | |
| dram_group_A_placements_front | |
| dram_group_A_signals | |
| dram_group_B_placements_front | |
| dram_group_B_signals | |
| dram_zq_resistor_note | |
| Absolute Maximum DC Rating - Voltage on VDD pin relative to Vss (VDD) | |
| Absolute Maximum DC Rating - Voltage on VDDQ pin relative to Vss (VDDQ) | |
| Absolute Maximum DC Rating - Voltage on VPP pin relative to Vss (VPP) | |
| Absolute Maximum DC Rating - Voltage on any pin relative to Vss (VIN, VOUT) | |
| Absolute Maximum DC Rating - Storage Temperature (TSTG) | |
| tREFI parameter - REFab Normal tREFI1 [0°C <= TCASE <= 85°C] | |
| tREFI parameter - REFab Normal tREFI1 [85°C < TCASE <= 95°C] | |
| tREFI parameter - REFab Fine Granularity tREFI2 [0°C <= TCASE <= 85°C] | |
| tREFI parameter - REFab Fine Granularity tREFI2 [85°C < TCASE <= 95°C] | |
| tREFI parameter - REFsb Fine Granularity tREFIsb [0°C <= TCASE <= 85°C] | |
| tREFI parameter - REFsb Fine Granularity tREFIsb [85°C < TCASE <= 95°C] | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Min | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Typ | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Max | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Z(f) Zmax 2MHz-10MHz | |
| Recommended DC Operating Condition - Device Supply Voltage (VDD) Z(f) Zmax 20MHz | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Min | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Typ | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Max | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Z(f) Zmax 2MHz-10MHz | |
| Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Z(f) Zmax 20MHz | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Min | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Typ | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Max | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Z(f) Zmax 2MHz-10MHz | |
| Recommended DC Operating Condition - Core Power Voltage (VPP) Z(f) Zmax 20MHz | |
| tAAmin (ns) [(top row)] | |
| tRCDmin/tRPmin (ns) [(top row)] | |
| Read CL Write CWL [(top row)] | |
| tCK(AVG) min [(top row)] | |
| tCK(AVG) max [(top row)] | |
| NOTE [(top row)] | |
| tAAmin (ns) [3200C] | |
| tRCDmin/tRPmin (ns) [3200C] | |
| Read CL Write CWL [3200C] | |
| tCK(AVG) min [3200C] | |
| tCK(AVG) max [3200C] | |
| tAAmin (ns) [3200BN/3200B] | |
| tRCDmin/tRPmin (ns) [3200BN/3200B] | |
| Read CL Write CWL [3200BN/3200B] | |
| tCK(AVG) min [3200BN/3200B] | |
| tCK(AVG) max [3200BN/3200B] | |
| tAAmin (ns) [3200AN] | |
| tRCDmin/tRPmin (ns) [3200AN] | |
| Read CL Write CWL [3200AN] | |
| tCK(AVG) [3200AN] | |
| tAAmin (ns) [3600C] | |
| tRCDmin/tRPmin (ns) [3600C] | |
| Read CL Write CWL [3600C] | |
| tCK(AVG) min [3600C] | |
| tCK(AVG) max [3600C] | |
| tAAmin (ns) [3600BN/3600B] | |
| tRCDmin/tRPmin (ns) [3600BN/3600B] | |
| Read CL Write CWL [3600BN/3600B] | |
| tCK(AVG) min [3600BN/3600B] | |
| tCK(AVG) max [3600BN/3600B] | |
| tAAmin (ns) [3600AN] | |
| tRCDmin/tRPmin (ns) [3600AN] | |
| Read CL Write CWL [3600AN] | |
| tCK(AVG) [3600AN] | |
| tAAmin (ns) [4000C] | |
| tRCDmin/tRPmin (ns) [4000C] | |
| Read CL Write CWL [4000C] | |
| tCK(AVG) min [4000C] | |
| tCK(AVG) max [4000C] | |
| tAAmin (ns) [4000BN/4000B] | |
| tRCDmin/tRPmin (ns) [4000BN/4000B] | |
| Read CL Write CWL [4000BN/4000B] | |
| tCK(AVG) min [4000BN/4000B] | |
| tCK(AVG) max [4000BN/4000B] | |
| tAAmin (ns) [4000AN] | |
| tRCDmin/tRPmin (ns) [4000AN] | |
| Read CL Write CWL [4000AN] | |
| tCK(AVG) [4000AN] | |
| tAAmin (ns) [4400C] | |
| tRCDmin/tRPmin (ns) [4400C] | |
| Read CL Write CWL [4400C] | |
| tCK(AVG) min [4400C] | |
| tCK(AVG) max [4400C] | |
| tAAmin (ns) [4400BN/4400B] | |
| tRCDmin/tRPmin (ns) [4400BN/4400B] | |
| Read CL Write CWL [4400BN/4400B] | |
| tCK(AVG) min [4400BN/4400B] | |
| tCK(AVG) max [4400BN/4400B] | |
| tAAmin (ns) [4400AN] | |
| tRCDmin/tRPmin (ns) [4400AN] | |
| Read CL Write CWL [4400AN] | |
| tCK(AVG) [4400AN] | |
| tAAmin (ns) [4800C] | |
| tRCDmin/tRPmin (ns) [4800C] | |
| Read CL Write CWL [4800C] | |
| tCK(AVG) min [4800C] | |
| tCK(AVG) max [4800C] | |
| tAAmin (ns) [4800BN] | |
| tRCDmin/tRPmin (ns) [4800BN] | |
| Read CL Write CWL [4800BN] | |
| tCK(AVG) min [4800BN] | |
| tCK(AVG) max [4800BN] | |
| tAAmin (ns) [4800B] | |
| tRCDmin/tRPmin (ns) [4800B] | |
| Read CL Write CWL [4800B] | |
| tCK(AVG) min [4800B] | |
| tCK(AVG) max [4800B] | |
| tAAmin (ns) [4800AN] | |
| tRCDmin/tRPmin (ns) [4800AN] | |
| Read CL Write CWL [4800AN] | |
| tCK(AVG) [4800AN] | |
| Module length (Front, overall) | |
| Height (secondary) | |
| Side thickness (max) | |
| Keep out area note (Detail D) | |
| Keep out dimension (Detail D) | |
| Keep out area note (Detail of Contacts) | |
| Module IDD basis | |
| module_configuration | |
| module_length_overall | |
| module_length_inner | |
| edge_to_first_feature | |
| key_notch_offset | |
| contact_span | |
| dim_2.10 | |
| dim_2.70 | |
| key_notch_position | |
| card_thickness | |
| card_thickness_qualifier | |
| fillet_radius | |
| dim_14.10 | |
| back_dim_17.10 | |
| registering_clock_driver_label | |
| spd_label | |
| ts_label | |
| detail_a_dim_3.35 | |
| detail_a_dim_8.00 | |
| detail_a_dim_11.00 | |
| detail_e_dim_2.10 | |
| detail_contacts_af_dim_0.85 | |
| detail_contacts_af_dim_0.60 | |
| detail_contacts_af_dim_1.50 | |
| detail_contacts_af_dim_0.2 | |
| detail_contacts_af_dim_0.20 | |
| detail_e_dim_5.95 | |
| detail_e_dim_3.85 | |
| detail_e_dim_4.30 | |
| detail_b_pins | |
| detail_b_dims | |
| detail_c_pins | |
| detail_c_dims | |
| detail_d_dims | |
| keep_out_callout_1 | |
| keep_out_callout_2 | |
| pin_callouts | |
| tolerance_note | |
| units_note |
