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SK hynix HMCG78MEBRAXXXN: rdimm, 16, 4800 | rackspecs

Server Memory

SK hynix HMCG78MEBRAXXXN

HMCG78MEBRAXXXN (SK hynix)

Memory Class

rdimm

Capacity Gb

16

Speed Mt S

4800

Memory Generation

ddr5

Specifications

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Other

Speed Mt S	4800
Capacity Gb	16
Rank Organization	16GB (1Rx8)
Memory Class	rdimm
Die Density Gb	16
Registered	true
Height Mm	30.75
Memory Generation	ddr5
Ecc	On-Die ECC
Product Name	DDR5 SDRAM RDIMM Based on 16Gb M-die
Pin Count	288
Voltage Vdd V	1.1
Act To Pre Command Period Tras Max
Act To Pre Command Period Tras Min
Bank Address In A Bg
Bg Address
Cas Latency
Cl Nrcd Nrp

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Vendor-specific

TEN DC Input High Voltage (VIH(DC)_TEN) - Min
TEN DC Input High Voltage (VIH(DC)_TEN) - Max
TEN DC Input Low Voltage (VIL(DC)_TEN) - Min
TEN DC Input Low Voltage (VIL(DC)_TEN) - Max
TEN AC Input Low Voltage (VIL(AC)_TEN) - Min
TEN AC Input Low Voltage (VIL(AC)_TEN) - Max
TEN Input signal Falling time (TF_input_TEN) - Max
TEN Input signal Rising time (TR_input_TEN) - Max
AC Input High Voltage (VIH(AC)_RESET) - Min
AC Input High Voltage (VIH(AC)_RESET) - Max
DC Input High Voltage (VIH(DC)_RESET) - Min
DC Input High Voltage (VIH(DC)_RESET) - Max
DC Input Low Voltage (VIL(DC)_RESET) - Min
DC Input Low Voltage (VIL(DC)_RESET) - Max
AC Input Low Voltage (VIL(AC)_RESET) - Min
AC Input Low Voltage (VIL(AC)_RESET) - Max
Rising time (TR_RESET) - Max
RESET pulse width (tPW_RESET) - Min
RON34Pd VOLdc=0.5*VDDQ Min
RON34Pd VOLdc=0.5*VDDQ Nom
RON34Pd VOLdc=0.5*VDDQ Max
RON34Pd VOMdc=0.8*VDDQ Min
RON34Pd VOMdc=0.8*VDDQ Max
RON34Pd VOHdc=0.95*VDDQ Min
RON34Pd VOHdc=0.95*VDDQ Max
RON34Pu VOLdc=0.5*VDDQ Min
RON34Pu VOLdc=0.5*VDDQ Max
RON34Pu VOMdc=0.8*VDDQ Min
RON34Pu VOMdc=0.8*VDDQ Max
RON34Pu VOHdc=0.95*VDDQ Min
RON34Pu VOHdc=0.95*VDDQ Max
RON48Pd VOLdc=0.5*VDDQ Min
RON48Pd VOLdc=0.5*VDDQ Max
RON48Pd VOMdc=0.8*VDDQ Min
RON48Pd VOMdc=0.8*VDDQ Max
RON48Pd VOHdc=0.95*VDDQ Min
RON48Pd VOHdc=0.95*VDDQ Max
RON48Pu VOLdc=0.5*VDDQ Min
RON48Pu VOLdc=0.5*VDDQ Max
RON48Pu VOMdc=0.8*VDDQ Min
RON48Pu VOMdc=0.8*VDDQ Max
RON48Pu VOHdc=0.95*VDDQ Min
RON48Pu VOHdc=0.95*VDDQ Max
Mismatch pull-up/pull-down MMPuPd Min
Mismatch pull-up/pull-down MMPuPd Max
Mismatch DQ-DQ within byte pull-up MMPudd Max
Mismatch DQ-DQ within byte pull-dn MMPddd Max
LB RON34Pd VOLdc=0.5*VDDQ Min
LB RON34Pd VOLdc=0.5*VDDQ Max
LB RON34Pd VOMdc=0.8*VDDQ Min
LB RON34Pd VOMdc=0.8*VDDQ Max
LB RON34Pd VOHdc=0.95*VDDQ Min
LB RON34Pd VOHdc=0.95*VDDQ Max
LB RON34Pu VOLdc=0.5*VDDQ Min
LB RON34Pu VOLdc=0.5*VDDQ Max
LB RON34Pu VOMdc=0.8*VDDQ Min
LB RON34Pu VOMdc=0.8*VDDQ Max
LB RON34Pu VOHdc=0.95*VDDQ Min
LB RON34Pu VOHdc=0.95*VDDQ Max
LB Mismatch MMPuPd Min
LB Mismatch MMPuPd Max
LB Mismatch LBDQS-LBDQ pull-up MMPudd Max
LB Mismatch LBDQS-LBDQ pull-dn MMPddd Max
tLBQSL Loopback LBDQS Output Low Time Min
tLBQSH Loopback LBDQS Output High Time Min
tLBDQSQ Loopback LBDQS to LBDQ Skew Min
tLBQH Loopback LBDQ Output Time from LBDQS Min
tLBDVW Loopback Data valid window Min
Alert_n RONPd VOLdc=0.1*VDDQ Min
Alert_n RONPd VOLdc=0.1*VDDQ Max
Alert_n RONPd VOMdc=0.8*VDDQ Min
Alert_n RONPd VOMdc=0.8*VDDQ Max
Alert_n RONPd VOHdc=0.95*VDDQ Min
Alert_n RONPd VOHdc=0.95*VDDQ Max
CT RONPd_CT VOBdc=0.2*VDDQ Max
CT RONPd_CT VOLdc=0.5*VDDQ Max
CT RONPd_CT VOMdc=0.8*VDDQ Max
CT RONPd_CT VOHdc=0.95*VDDQ Max
CT RONPu_CT VOBdc=0.2*VDDQ Max
CT RONPu_CT VOLdc=0.5*VDDQ Max
CT RONPu_CT VOMdc=0.8*VDDQ Max
CT RONPu_CT VOHdc=0.95*VDDQ Max
VOH Output high measurement level (for output SR)
VOL Output low measurement level (for output SR)
LB VOH Output high measurement level (for output SR)
LB VOL Output low measurement level (for output SR)
SRQse Single ended output slew rate Min
SRQse Single ended output slew rate Max
TxEW_DQ_SES_1UI - Eye Width (skew DQ/DQS 1UI), Min
TxEH_DQ_SES_2UI - Eye Height (skew DQ/DQS 2UI), Min
TxEW_DQ_SES_2UI - Eye Width (skew DQ/DQS 2UI), Min
TxEH_DQ_SES_3UI - Eye Height (skew DQ/DQS 3UI), Min
VOHdiff Differential output high measurement level (for output SR)
TxEW_DQ_SES_3UI - Eye Width (skew DQ/DQS 3UI), Min
VOLdiff Differential output low measurement level (for output SR)
SRQdiff Differential output slew rate Min
SRQdiff Differential output slew rate Max
tTx_DQS_1UI_Rj_NoBUJ Rj RMS 1-UI without BUJ Max
tTx_DQS_1UI_Dj_NoBUJ Dj pp 1-UI without BUJ Max
tTx_DQS_NUI_Rj_NoBUJ Rj RMS N-UI without BUJ (1<N<4) Max
tTx_DQS_NUI_Dj_NoBUJ Dj pp N-UI without BUJ (1<N<4) Max
tTx_DQ_1UI_Rj_NoBUJ Rj RMS 1-UI without BUJ Max
tTx_DQ_1UI_Dj_NoBUJ Dj pp 1-UI without BUJ Max
TxEH_DQ_SES_4UI - Eye Height (skew DQ/DQS 4UI), Min
tTx_DQ_NUI_Rj_NoBUJ Rj RMS N-UI without BUJ (1<N<4) Max
tTx_DQ_NUI_Dj_NoBUJ Dj pp N-UI without BUJ (1<N<4) Max
tTx_DQS2DQ Delay of any data lane relative to strobe lane Min
tTx_DQS2DQ Delay of any data lane relative to strobe lane Max
Tx DQ Rj max value note
TxEH_DQ_SES_1UI Eye Height skew 1UI Min
TxEW_DQ_SES_1UI Eye Width skew 1UI Min
TxEH_DQ_SES_2UI Eye Height skew 2UI Min
TxEW_DQ_SES_2UI Eye Width skew 2UI Min
TxEH_DQ_SES_3UI Eye Height skew 3UI Min
TxEW_DQ_SES_3UI Eye Width skew 3UI Min
TxEH_DQ_SES_4UI Eye Height skew 4UI Min
TxEW_DQ_SES_4UI Eye Width skew 4UI Min
TxEH_DQ_SES_5UI Eye Height skew 5UI Min
TxEW_DQ_SES_4UI - Eye Width (skew DQ/DQS 4UI), Min
TxEW_DQ_SES_5UI Eye Width skew 5UI Min
TCASE for IDD/IDDQ/IPP measurement
MID-LEVEL definition (VREF)
Burst Length for IDD patterns
IDD6N Self Refresh Normal Temp Range TCASE
IDD6E Self Refresh Extended Temp Range TCASE
Internal read command to first data (tAA) min
ACT to internal read or write delay time (tRCD) min
Row Precharge Time (tRP) min
ACT to ACT or REF command period (tRC) min
3200C tAAmin
3200C Read CL / Write CWL
3200C tCK(AVG) min
3200C tCK(AVG) max
3200BN/3200B tAAmin
3200BN/3200B tRPmin
3200BN/3200B Read CL / Write CWL
3200BN/3200B tCK(AVG) min
3200BN/3200B tCK(AVG) max
3200AN tAAmin
3200AN tRPmin
3200AN Read CL / Write CWL
3200AN tCK(AVG)
3200AN (15.000) tAA/tRP
3600C tAAmin
3600C tRPmin
3600C Read CL / Write CWL
3600C tCK(AVG) min
3600C tCK(AVG) max
3600BN/3600B tAAmin
3600BN/3600B tRPmin
3600BN/3600B Read CL / Write CWL
3600BN/3600B tCK(AVG) min
3600BN/3600B tCK(AVG) max
3600AN tAA/tRP
3600AN Read CL / Write CWL
3600AN tCK(AVG)
4000C tAAmin
4000C tRPmin
4000C Read CL / Write CWL
4000C tCK(AVG) min
4000C tCK(AVG) max
4000BN/4000B tAAmin
4000BN/4000B tRPmin
4000BN/4000B Read CL / Write CWL
4000BN/4000B tCK(AVG) min
4000BN/4000B tCK(AVG) max
4000AN tAA/tRP
4000AN Read CL / Write CWL
4000AN tCK(AVG)
4400C tAAmin
4400C tRPmin
4400C Read CL / Write CWL
4400C tCK(AVG) min
4400C tCK(AVG) max
4400BN/4400B tAA/tRP
4400BN/4400B Read CL / Write CWL
4400BN/4400B tCK(AVG) min
4400BN/4400B tCK(AVG) max
4400AN tAA/tRP
4400AN Read CL / Write CWL
4400AN tCK(AVG)
Supported CL
3200BN/3200B tAA/tRP
3200AN tAA/tRP
3600C tAA/tRP
3600BN/3600B tAA/tRP
4000BN/4000B tAA/tRP
4800C tAA/tRP
4800C Read CL / Write CWL
4800C tCK(AVG) min
4800C tCK(AVG) max
4800BN tAA/tRP
4800BN Read CL / Write CWL
4800BN tCK(AVG) min
4800BN tCK(AVG) max
4800B tAAmin
4800B tRPmin
4800B Read CL / Write CWL
4800B tCK(AVG) min
4800B tCK(AVG) max
4800AN tAA/tRP
4800AN Read CL / Write CWL
4800AN tCK(AVG)
Specification section
Vnoise_Stressed_Eye_Golden_Ref_Channel_1 - Injected voltage noise (PRBS23 / 2.1 GHz), Min
TxEH_DQ_SES_5UI - Eye Height (skew DQ/DQS 5UI), Min
TxEW_DQ_SES_5UI - Eye Width (skew DQ/DQS 5UI), Min
Vnoise_Stressed_Eye_Golden_Ref_Channel_1 - Injected voltage noise, Max
Module IDD basis note
Module type / drawing title
Module overall width (Front, outer)
Module width (Front, inner)
Module height (Front)
Dimension
Contact segment dimension
Notch / radius dimension
Side / contact pitch
Side / max thickness
Component label
Detail A,F dimension
Detail B dimension
Detail B pin callout
Detail C dimension
Detail C pin callout
Detail D keep-out note
Detail D pin callout
Detail E max dimension
Detail E keep-out note
Detail labels present
Based on
Manufacturer
tREFI1 (REFab Normal), 0°C<=TCASE<=85°C
tREFI1 (REFab Normal), 85°C<TCASE<=95°C
tREFI2 (REFab Fine Granularity), 0°C<=TCASE<=85°C
tREFI2 (REFab Fine Granularity), 85°C<TCASE<=95°C
tREFIsb (REFsb Fine Granularity), 0°C<=TCASE<=85°C
tREFIsb (REFsb Fine Granularity), 85°C<TCASE<=95°C
Device Supply Voltage VDD (Recommended DC, Typ)
Device Supply Voltage VDD (Recommended DC, Min)
Device Supply Voltage VDD (Recommended DC, Max)
Supply Voltage for I/O VDDQ (Recommended DC, Typ)
Supply Voltage for I/O VDDQ (Recommended DC, Min)
Supply Voltage for I/O VDDQ (Recommended DC, Max)
Core Power Voltage VPP (Recommended DC, Typ)
Core Power Voltage VPP (Recommended DC, Min)
Core Power Voltage VPP (Recommended DC, Max)
Z(f) Spec Zmax (DC to 2MHz / 2MHz to 10MHz) for VDD/VDDQ/VPP
Z(f) Spec Zmax (Freq: 20MHz) for VDD/VDDQ/VPP
Rx Mask voltage - p-p (VciVW) Max
Rx Timing Window (TcIVW) Max
Input Slew Rate over VcIVW (SRIN_cIVW) Min
Input Slew Rate over VcIVW (SRIN_cIVW) Max
DRAM Reference clock frequency (tCK) Min
DRAM Reference clock frequency (tCK) Max
Duty Cycle Error (tCK_Duty_UI_Error) Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) Max
Golden_Ref_Channel_1_Characteristics
Rj RMS value of N-UI Jitter, N=2,3 (tCK_NUI_Rj_NoBUJ) Max
tCT_IS, Min
tCT_Enable, Min
tCT_Valid, Max
Dj pp value of N-UI Jitter, N=2,3 (tCK_NUI_Dj_NoBUJ) Max
VIH(AC)_TEN - TEN AC Input High Voltage, Min
Tj value of N-UI Jitter, N=2,3 (tCK_NUI_Tj_NoBUJ) Max
Rj RMS value of N-UI Jitter, N=4..30 (tCK_NUI_Rj_NoBUJ)
Dj pp value of N-UI Jitter, N=4..30 (tCK_NUI_Dj_NoBUJ)
Tj value of N-UI Jitter, N=4..30 (tCK_NUI_Tj_NoBUJ)
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Max
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) Max
VIH(DC)_TEN - TEN DC Input High Voltage, Min
Differential input high measurement level CK (VIHdiffCK)
Differential input low measurement level CK (VILdiffCK)
VIL(DC)_TEN - TEN DC Input Low Voltage, Max
VIL(AC)_TEN - TEN AC Input Low Voltage, Max
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Max
DQ Timing Width (tRx_DQ_tMargin) Min
TF_input_TEN - TEN Input signal Falling time, Max
TR_input_TEN - TEN Input signal Rising time, Max
VIH(AC)_RESET - AC Input High Voltage, Min
VIH(DC)_RESET - DC Input High Voltage, Min
VIL(DC)_RESET - DC Input Low Voltage, Max
VIL(AC)_RESET - AC Input Low Voltage, Max
TR_RESET - Rising time, Max
Degradation of timing width with DCD injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD) Max
Degradation of timing width with Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_Rj) Max
tPW_RESET - RESET pulse width, Min
RON34Pu @ VOMdc=0.8*VDDQ, Min
RON34Pu @ VOHdc=0.95*VDDQ, Min
RON48Pd @ VOMdc=0.8*VDDQ, Min
RON48Pd @ VOHdc=0.95*VDDQ, Max
RON48Pu @ VOMdc=0.8*VDDQ, Min
RON48Pu @ VOHdc=0.95*VDDQ, Min
Degradation of timing width with both DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max
Applied DCD to the DQS (tRx_DQS_DCD) Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) Max
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) Max
Differential input high measurement level DQS (VIHdiffDQS)
Differential input low measurement level DQS (VILdiffDQS)
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max
Eye height of stressed eye for Golden Reference Channel 1 Max
Eye width of stressed eye Golden Reference Channel 1 Max
Vswing stress to meet above data eye Max
Injected sinusoidal jitter at 200 MHz (Sj) Max
Injected Random wide band (10 MHz-1 GHz) Jitter (Rj) Max
Injected voltage noise (PRBS23 / 2.1 GHz) (Vnoise) Max
CT Mode AC parameter tCT_IS Min
CT Mode AC parameter tCT_Enable Min
CT Mode AC parameter tCT_Valid Max
RON34Pd VOLdc=0.5*VDDQ (Output Driver DC) Min/Nom/Max
RON34Pd VOMdc=0.8*VDDQ Min/Nom/Max
RON34Pd VOHdc=0.95*VDDQ Min/Nom/Max
RON34Pu VOLdc=0.5*VDDQ Min/Nom/Max
RON34Pu VOMdc=0.8*VDDQ Min/Nom/Max
RON34Pu VOHdc=0.95*VDDQ Min/Nom/Max
RON48Pd VOLdc=0.5*VDDQ Min/Nom/Max
RON48Pd VOMdc=0.8*VDDQ Min/Nom/Max
RON48Pd VOHdc=0.95*VDDQ Min/Nom/Max
RON48Pu VOLdc=0.5*VDDQ Min/Nom/Max
RON48Pu VOMdc=0.8*VDDQ Min/Nom/Max
RON48Pu VOHdc=0.95*VDDQ Min/Nom/Max
MMPuPd - Mismatch pull-up/pull-down @ VOMdc=0.8*VDDQ, Min
Mismatch between pull-up and pull-down (MMPuPd) VOMdc=0.8*VDDQ Min/Max
Mismatch DQ-DQ within byte variation pull-up (MMPudd) Max
Mismatch DQ-DQ within byte variation pull-dn (MMPddd) Max
Loopback RON34Pd VOLdc=0.5*VDDQ Min/Nom/Max
Loopback RON34Pd VOMdc=0.8*VDDQ Min/Nom/Max
Loopback RON34Pd VOHdc=0.95*VDDQ Min/Nom/Max
Loopback RON34Pu VOLdc=0.5*VDDQ Min/Nom/Max
Loopback RON34Pu VOMdc=0.8*VDDQ Min/Nom/Max
Loopback RON34Pu VOHdc=0.95*VDDQ Min/Nom/Max
Loopback Mismatch pull-up/pull-down (MMPuPd) Min/Max
Loopback Mismatch LBDQS-LBDQ within device pull-up (MMPudd) Max
Loopback Mismatch LBDQS-LBDQ within device pull-dn (MMPddd) Max
Loopback LBDQS Output Low Time (tLBQSL) Min
Loopback LBDQS Output High Time (tLBQSH) Min
Loopback LBDQS to LBDQ Skew (tLBDQSQ) Min
Loopback LBDQ Output Time from LBDQS (tLBQH) Min
Loopback Data valid window (tLBDVW) Min
Alert_n RONPd VOLdc=0.1*VDDQ Min/Max
Alert_n RONPd VOMdc=0.8*VDDQ Min/Max
Alert_n RONPd VOHdc=0.95*VDDQ Min/Max
CT Mode RONPd_CT VOBdc=0.2*VDDQ Max
CT Mode RONPd_CT VOLdc=0.5*VDDQ Max
CT Mode RONPd_CT VOMdc=0.8*VDDQ Max
CT Mode RONPd_CT VOHdc=0.95*VDDQ Max
CT Mode RONPu_CT VOBdc=0.2*VDDQ Max
CT Mode RONPu_CT VOLdc=0.5*VDDQ Max
CT Mode RONPu_CT VOMdc=0.8*VDDQ Max
CT Mode RONPu_CT VOHdc=0.95*VDDQ Max
Single-ended Output high measurement level (VOH)
Single-ended Output low measurement level (VOL)
MID-LEVEL definition for IDD/IPP/IDDQ measurement
TCASE for IDD/IPP/IDDQ measurement
Burst Length (BL) for IDD patterns
Single-ended Output high measurement level for Loopback (VOH)
Single-ended Output low measurement level for Loopback (VOL)
Single ended output slew rate (SRQse) Min
Single ended output slew rate (SRQse) Max
IDD0 current definition
Differential output high measurement level (VOHdiff)
Differential output low measurement level (VOLdiff)
Differential output slew rate (SRQdiff) Min
Differential output slew rate (SRQdiff) Max
MMPudd - Mismatch DQ-DQ within byte pull-up @ VOMdc=0.8*VDDQ, Max
MMPddd - Mismatch DQ-DQ within byte pull-dn @ VOMdc=0.8*VDDQ, Max
RON34Pd (Loopback) @ VOLdc=0.5*VDDQ, Min
Tx DQS Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) Max
Tx DQS Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) Max
RON34Pd (Loopback) @ VOHdc=0.95*VDDQ, Max
Tx DQS Rj RMS Value of N-UI jitter without BUJ (1<N<4) (tTx_DQS_NUI_Rj_NoBUJ) Max
RON34Pu (Loopback) @ VOLdc=0.5*VDDQ, Max
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) (tTx_DQS_NUI_Dj_NoBUJ) Max
MMPuPd (Loopback) - Mismatch pull-up/pull-down, Min
MMPudd (Loopback) - Mismatch LBDQS-LBDQ pull-up, Max
Tx DQ Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) Max
Tx DQ Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) Max
Tx DQ Rj RMS of N-UI jitter without BUJ (1<N<4) (tTx_DQ_NUI_Rj_NoBUJ) Max
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) (tTx_DQ_NUI_Dj_NoBUJ) Max
Tx DQ Delay of any data lane relative to strobe lane (tTx_DQS2DQ) Min
Tx DQ Delay of any data lane relative to strobe lane (tTx_DQS2DQ) Max
MMPddd (Loopback) - Mismatch LBDQS-LBDQ pull-dn, Max
tLBQSL - Loopback LBDQS Output Low Time, Min
Tx DQ Eye Width at transmitter, skew DQ-DQS 1UI (TxEW_DQ_SES_1UI) Min
tLBQSH - Loopback LBDQS Output High Time, Min
tLBDQSQ - Loopback LBDQS to LBDQ Skew, Min
tLBQH - Loopback LBDQ Output Time from LBDQS, Min
IDDQ0 current definition
IPP0 current definition
IDD0F current definition
IDD2N current definition
IDD2NT current definition
IDD2P current definition
IDD3N current definition
IDD3P current definition
IDD4R current definition
IDD4RC current definition
IDD4W current definition
Tx DQ Eye Height at transmitter, skew DQ-DQS 1UI (TxEH_DQ_SES_1UI) Min
IDD4WC current definition
Tx DQ Eye Width at transmitter, skew DQ-DQS 2UI (TxEW_DQ_SES_2UI) Min
Tx DQ Eye Width at transmitter, skew DQ-DQS 3UI (TxEW_DQ_SES_3UI) Min
IDD5B current definition
Tx DQ Eye Height at transmitter, skew DQ-DQS 2UI/3UI/4UI/5UI (TxEH_DQ_SES) Min
Tx DQ Eye Width at transmitter, skew DQ-DQS 4UI/5UI (TxEW_DQ_SES) Min
IDD5F current definition
IDD0 - Operating One Bank Active-Precharge Current (symbol/definition)
IDD0F - Operating Four Bank Active-Precharge Current (symbol/definition)
IDD2N - Precharge Standby Current (symbol/definition)
IDD2NT - Precharge Standby Non-Target Command Current (symbol/definition)
IDD2P - Precharge Power-Down (symbol/definition)
IDD3N - Active Standby Current (symbol/definition)
IDD3P - Active Power-Down Current (symbol/definition)
IDD4R - Operating Burst Read Current (symbol/definition)
IDD4W - Operating Burst Write Current (symbol/definition)
IDD5C current definition
IDD5B - Burst Refresh Current Normal Refresh Mode (symbol/definition)
tLBDVW - Loopback Data valid window (tLBQH-tLBDQSQ) per UI per DRAM, Min
IDD5F - Burst Refresh Current Fine Granularity Refresh Mode (symbol/definition)
IDD5C - Burst Refresh Current Same Bank Refresh Mode (symbol/definition)
RONPd (Alert_n) @ VOLdc=0.1*VDDQ, Min
IDD6N - Self Refresh Current Normal Temperature Range (symbol/definition)
IDD6E - Self Refresh Current Extended Temperature Range (symbol/definition)
RONPd (Alert_n) @ VOMdc=0.8*VDDQ, Min
IDD7 - Operating Bank Interleave Read Current (symbol/definition)
RONPd (Alert_n) @ VOHdc=0.95*VDDQ, Min
IDD8 - Maximum Power Saving Deep Power Down Current (symbol/definition)
IDD9 - MBIST Current (Optional) (symbol/definition)
ACT to PRE command period (tRAS)
Supported Frequency Down Bin - tAAmin (ns)
Frequency Down Bin tAAmin / tRCDmin / tRPmin
General tolerance on all dimensions unless otherwise stated
Front overall width
Front width (inner)
Front edge to first feature
Front left segment width
Front right segment width
Module height (top to contact, front view)
Lower feature height (front view)
Front right edge feature spacing
Back overall width
Back width (inner)
Back module height
Back feature dimension
Back feature dimension (2)
Notch fillet radius
Side PCB thickness (max)
RONPd_CT @ VOBdc=0.2*VDDQ, Max
Detail A - Registering Clock Driver
Detail A dimension (2)
Detail A component - SPD
Detail A component - TS
Detail of Contacts A, F - contact height
Detail of Contacts A, F - contact pitch
Detail of Contacts A, F - dimension
Detail of Contacts A, F - dimension (2)
Detail of Contacts A, F - dimension (3)
Detail of Contacts A, F - dimension (4)
Detail of Contacts A, F - dimension (5)
Detail of Contacts A, F - dimension (6)
Detail of Contacts B - dimension
Detail of Contacts B - dimension (2)
Detail of Contacts B - dimension (3)
Detail of Contacts B - dimension (4)
Detail of Contacts B - pin callout
Detail B - pin callout
Detail of Contacts C - dimension
Detail of Contacts C - dimension (2)
Detail of Contacts C - dimension (3)
Detail of Contacts C - dimension (4)
Detail of Contacts C - pin callout
Detail C - pin callout
Detail of Contacts D - dimension
Detail of Contacts D - dimension (2)
Detail of Contacts D - contact height
Detail of Contacts D - contact pitch
Detail of Contacts D - non-metalized keep out area
Detail of Contacts D - keep out max dimension
RONPd_CT @ VOLdc=0.5*VDDQ, Max
Detail of Contacts D - keep out max dimension (2)
Detail of Contacts D - keep out max dimension (3)
RONPd_CT @ VOMdc=0.8*VDDQ, Max
RONPd_CT @ VOHdc=0.95*VDDQ, Max
RONPu_CT @ VOBdc=0.2*VDDQ, Max
RONPu_CT @ VOLdc=0.5*VDDQ, Max
RONPu_CT @ VOMdc=0.8*VDDQ, Max
RONPu_CT @ VOHdc=0.95*VDDQ, Max
VOH - Output high measurement level (for output SR)
VOL - Output low measurement level (for output SR)
VOH - Output high measurement level (Loopback signals)
VOL - Output low measurement level (Loopback signals)
SRQse - Single ended output slew rate, Min
SRQse - Single ended output slew rate, Max
VOHdiff - Differential output high measurement level (for output SR)
VOLdiff - Differential output low measurement level (for output SR)
SRQdiff - Differential output slew rate, Min
SRQdiff - Differential output slew rate, Max
tTx_DQS_1UI_Rj_NoBUJ - Rj RMS of 1-UI Jitter without BUJ, Max
tTx_DQS_1UI_Dj_NoBUJ - Dj pp Value of 1-UI Jitter without BUJ, Max
tTx_DQS_NUI_Rj_NoBUJ (1<N<4) - Rj RMS of N-UI jitter without BUJ, Max
tTx_DQS_NUI_Dj_NoBUJ (1<N<4) - Dj pp Value of N-UI Jitter without BUJ, Max
tTx_DQ_1UI_Rj_NoBUJ - Rj RMS of 1-UI jitter without BUJ, Max
tTx_DQ_1UI_Dj_NoBUJ - Dj pp 1-UI jitter without BUJ, Max
tTx_DQ_NUI_Rj_NoBUJ (1<N<4) - Rj RMS of N-UI jitter without BUJ, Max
tTx_DQ_NUI_Dj_NoBUJ (1<N<4) - Dj pp N-UI jitter without BUJ, Max
Detail of Contacts E - keep out max dimension
Detail of Contacts E - keep out max dimension (2)
Detail of Contacts E - keep out max dimension (3)
Detail E - dimension
Detail E - dimension (2)
Pin 1 callout
tREFI1 (REFab, Normal, 0C<=TCASE<=85C)
tREFI1 (REFab, Normal, 85C<TCASE<=95C)
tREFI2 (REFab, Fine Granularity, 0C<=TCASE<=85C)
tREFI2 (REFab, Fine Granularity, 85C<TCASE<=95C)
tREFIsb (REFsb, Fine Granularity, 0C<=TCASE<=85C)
tREFIsb (REFsb, Fine Granularity, 85C<TCASE<=95C)
VDD - Device Supply Voltage, Min
VDD - Device Supply Voltage, Typ
VDD - Device Supply Voltage, Max
VDD - Z(f) DC to 2MHz Zmax
VDD - Z(f) 20MHz Zmax
VDDQ - Supply Voltage for I/O, Min
VDDQ - Supply Voltage for I/O, Typ
VDDQ - Supply Voltage for I/O, Max
VDDQ - Z(f) DC to 2MHz Zmax
VDDQ - Z(f) 20MHz Zmax
VPP - Core Power Voltage, Min
VPP - Core Power Voltage, Typ
VPP - Core Power Voltage, Max
VPP - Z(f) DC to 2MHz Zmax
VPP - Z(f) 20MHz Zmax
VciVW - Rx Mask voltage p-p, Max
TcIVW - Rx Timing Window, Max
VIHL_AC - CA Input Pulse Amplitude
TcIPW - CA Input Pulse Width
SRIN_cIVW - Input Slew Rate over VcIVW, Min
SRIN_cIVW - Input Slew Rate over VcIVW, Max
tCK_Duty_UI_Error - Duty Cycle Error, Max
tCK_1UI_Rj_NoBUJ - Rj RMS 1-UI Jitter, Max
tCK_1UI_Dj_NoBUJ - Dj pp 1-UI Jitter, Max
tCK_1UI_Tj_NoBUJ - Tj 1-UI Jitter, Max
tCK_NUI_Rj_NoBUJ (N=2,3) - Rj RMS, Max
tCK_NUI_Dj_NoBUJ (N=2,3) - Dj pp, Max
tCK_NUI_Tj_NoBUJ (N=2,3) - Tj, Max
tCK_NUI_Rj_NoBUJ (N=4..30) - Rj RMS, Max
tCK_NUI_Dj_NoBUJ (N=4..30) - Dj pp, Max
tCK_NUI_Tj_NoBUJ (N=4..30) - Tj, Max
VIX_CK_Ratio - Clock differential input crosspoint voltage ratio, Max
VRx_CK - Input Clock Voltage Sensitivity (differential pp), Max
VIHdiffCK - Differential input high measurement level (CK_t, CK_c)
VILdiffCK - Differential input low measurement level (CK_t, CK_c)
SRIdiff_CK - Differential Input Slew Rate for CK_t, CK_c, Min
SRIdiff_CK - Differential Input Slew Rate for CK_t, CK_c, Max
tRx_DQ_tMargin - DQ Timing Width, Min
dtRx_DQ_tMargin_DQS_DCD - Degradation w/ DCD injection, Max
dtRx_DQ_tMargin_DQS_Rj - Degradation w/ Rj injection, Max
dtRx_DQ_tMargin_DQS_DCD_Rj - Degradation w/ DCD and Rj, Max
tRx_DQS2DQ - Delay of data lane relative to DQS crossing, Min
tRx_DQS2DQ - Delay of data lane relative to DQS crossing, Max
tRx_DQS2DQ - Delay, Max
tRx_DQS_DCD - Applied DCD to the DQS, Max
tRx_DQS_Rj - Applied Rj RMS to the DQS, Max
tTx_DQS2DQ - Delay of any data lane relative to strobe lane, Min
tRx_DQS_DCD_Rj - Applied DCD and Rj RMS to the DQS, Max
VRx_DQS - DQS Rx Input Voltage Sensitivity (differential pp), Max
VIX_DQS_Ratio - DQS differential input crosspoint voltage ratio, Max
VIHdiffDQS - Differential input high measurement level (DQS_t, DQS_c)
tTx_DQS2DQ - Delay of any data lane relative to strobe lane, Max
VILdiffDQS - Differential input low measurement level (DQS_t, DQS_c)
SRIdiff_DQS - Differential Input Slew Rate for DQS_t, DQS_c
VRx_DQ - Minimum DQ Rx input voltage sensitivity applied around Vref, Max
RxEH_Stressed_Eye_Golden_Ref_Channel_1 - Eye height of stressed eye, Max
RxEH_Stressed_Eye_Golden_Ref_Channel_1 - Eye height, Max
RxEW_Stressed_Eye_Golden_Ref_Channel_1 - Eye width of stressed eye, Max
Vswing_Stressed_Eye_Golden_Ref_Channel_1 - Vswing stress, Max
Sj_Stressed_Eye_Golden_Ref_Channel_1 - Injected sinusoidal jitter at 200 MHz, Min
Sj_Stressed_Eye_Golden_Ref_Channel_1 - Injected sinusoidal jitter at 200 MHz, Max
Rj_Stressed_Eye_Golden_Ref_Channel_1 - Injected Random wide band (10 MHz-1 GHz) Jitter, Min
Rj_Stressed_Eye_Golden_Ref_Channel_1 - Injected Random wide band Jitter, Max
Base Die
Intended Use
DRAM VDD/VDDQ
DRAM VPP
Bank Configuration (x4/x8)
Bank Configuration (x16)
Bank Groups
Burst Length Support
Feature
Organization
Page size
Voltage on VDD pin relative to Vss (Absolute Maximum)
Voltage on VDDQ pin relative to Vss (Absolute Maximum)
Voltage on VPP pin relative to Vss (Absolute Maximum)
Voltage on any pin relative to Vss (VIN, VOUT, Absolute Maximum)
Storage Temperature (TSTG, Absolute Maximum)
tREFI1 REFab Normal, 0°C <= TCASE <= 85°C
tREFI1 REFab Normal, 85°C < TCASE <= 95°C
tREFI2 REFab Fine Granularity, 0°C <= TCASE <= 85°C
tREFI2 REFab Fine Granularity, 85°C < TCASE <= 95°C
tREFIsb REFsb Fine Granularity, 0°C <= TCASE <= 85°C
tREFIsb REFsb Fine Granularity, 85°C < TCASE <= 95°C
Device Supply Voltage VDD Min (Recommended DC Operating)
Device Supply Voltage VDD Typ (Recommended DC Operating)
Device Supply Voltage VDD Max (Recommended DC Operating)
VDD Z(f) Spec 2MHz to 10MHz (Zmax)
VDD Z(f) Spec 20MHz (Zmax)
Supply Voltage for I/O VDDQ Min (Recommended DC Operating)
Supply Voltage for I/O VDDQ Typ
Supply Voltage for I/O VDDQ Max
VDDQ Z(f) Spec 2MHz to 10MHz (Zmax)
VDDQ Z(f) Spec 20MHz (Zmax)
Core Power Voltage VPP Min (Recommended DC Operating)
Core Power Voltage VPP Typ
Core Power Voltage VPP Max
VPP Z(f) Spec 2MHz to 10MHz (Zmax)
VPP Z(f) Spec 20MHz (Zmax)
Rx Mask voltage p-p (VciVW) Max, DDR5-3200
Rx Mask voltage p-p (VciVW) Max, DDR5-3600
Rx Mask voltage p-p (VciVW) Max, DDR5-4000
Rx Mask voltage p-p (VciVW) Max, DDR5-4400
Rx Mask voltage p-p (VciVW) Max, DDR5-4800
Rx Timing Window (TcIVW) Max, DDR5-3200 to 4800
CA Input Pulse Amplitude (VIHL_AC), DDR5-3200
CA Input Pulse Amplitude (VIHL_AC), DDR5-3600
CA Input Pulse Amplitude (VIHL_AC), DDR5-4000
CA Input Pulse Amplitude (VIHL_AC), DDR5-4400
CA Input Pulse Amplitude (VIHL_AC), DDR5-4800
CA Input Pulse Width (TcIPW), DDR5-3200 to 4800
Input Slew Rate over VcIVW (SRIN_cIVW) Min, DDR5-3200 to 4800
Input Slew Rate over VcIVW (SRIN_cIVW) Max, DDR5-3200 to 4800
DRAM Reference clock frequency (tCK) Min, DDR5-3200 to 4800
DRAM Reference clock frequency (tCK) Max, DDR5-3200 to 4800
Duty Cycle Error (tCK_Duty_UI_Error) Max, DDR5-3200 to 4800
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) Max, DDR5-3200 to 4800
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) Max, DDR5-3200 to 4800
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) Max, DDR5-3200 to 4800
Rj RMS value of N-UI Jitter N=2,3 (tCK_NUI_Rj_NoBUJ) Max, DDR5-3200 to 4800
Dj pp value of N-UI Jitter N=2,3 (tCK_NUI_Dj_NoBUJ) Max, DDR5-3200 to 4800
Tj value of N-UI Jitter N=2,3 (tCK_NUI_Tj_NoBUJ) Max, DDR5-3200 to 4800
Rj RMS value of N-UI Jitter N=4..30 (tCK_NUI_Rj_NoBUJ) Max, DDR5-3200 to 4800
Dj pp value of N-UI Jitter N=4..30 (tCK_NUI_Dj_NoBUJ) Max, DDR5-3200 to 4800
Tj value of N-UI Jitter N=4..30 (tCK_NUI_Tj_NoBUJ) Max, DDR5-3200 to 4800
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Max, DDR5-3200 - 4800
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Max, DDR5-6800 - 8400
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max, DDR5-3200
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max, DDR5-3600
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max, DDR5-4000
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max, DDR5-4400
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max, DDR5-4800
Differential input high measurement level CK_t,CK_c (VIHdiffCK), DDR5 3200-6400
Differential input low measurement level CK_t,CK_c (VILdiffCK), DDR5 3200-6400
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Min, DDR5-3200 to 4800
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Max, DDR5-3200 to 4800
DQ Timing Width (tRx_DQ_tMargin) Min, DDR5-3200
DQ Timing Width (tRx_DQ_tMargin) Min, DDR5-3600
DQ Timing Width (tRx_DQ_tMargin) Min, DDR5-4000
DQ Timing Width (tRx_DQ_tMargin) Min, DDR5-4400
DQ Timing Width (tRx_DQ_tMargin) Min, DDR5-4800
Degradation of timing width with DCD injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD) Max, DDR5-3200 to 4800
Degradation of timing width with Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_Rj) Max, DDR5-3200 to 4800
Degradation of timing width with both DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) Max, DDR5-3200 to 4800
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Min, DDR5-3200 to 4800
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max, DDR5-3200
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max, DDR5-3600
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max, DDR5-4000
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max, DDR5-4400
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max, DDR5-4800
Applied DCD to the DQS (tRx_DQS_DCD) Max, DDR5-3200 to 4800
Applied Rj RMS to the DQS (tRx_DQS_Rj) Max, DDR5-3200 to 4800
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) Max, DDR5-3200 to 4800
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max, DDR5-3200
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max, DDR5-3600
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max, DDR5-4000
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max, DDR5-4400
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max, DDR5-4800
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) Max, DDR5-3200 - 4800
Differential input high measurement level DQS_t,DQS_c (VIHdiffDQS), DDR5 3200-6400
Differential input low measurement level DQS_t,DQS_c (VILdiffDQS), DDR5 3200-6400
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS), DDR5-3200 to 4800
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max, DDR5-3200
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max, DDR5-3600
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max, DDR5-4000
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max, DDR5-4400-6400
Eye height of stressed eye Golden Reference Channel 1 (RxEH) Max, DDR5-3200
Eye height of stressed eye Golden Reference Channel 1 (RxEH) Max, DDR5-3600
Eye height of stressed eye Golden Reference Channel 1 (RxEH) Max, DDR5-4000
Eye height of stressed eye Golden Reference Channel 1 (RxEH) Max, DDR5-4400
Eye height of stressed eye Golden Reference Channel 1 (RxEH) Max, DDR5-4800
Eye width of stressed eye Golden Reference Channel 1 (RxEW) Max, DDR5-3200 to 4800
Vswing stress to meet above data eye (Vswing_Stressed_Eye) Max, DDR5-3200 to 4800
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye) Min, DDR5-3200 to 4800
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye) Max, DDR5-3200 to 4800
Injected Random wide band (10MHz-1GHz) Jitter (Rj_Stressed_Eye) Min, DDR5-3200 to 4800
Injected Random wide band (10MHz-1GHz) Jitter (Rj_Stressed_Eye) Max, DDR5-3200 to 4800
Injected voltage noise as PRBS23 or at 2.1 GHz (Vnoise_Stressed_Eye) Min, DDR5-3200 to 4800
Injected voltage noise as PRBS23 or at 2.1 GHz (Vnoise_Stressed_Eye) Max, DDR5-3200 to 4800
Golden Reference Channel 1 Characteristics (DDR5-3200 to 4800)
Connectivity Test Mode tCT_IS Min
Connectivity Test Mode tCT_Enable Min
Connectivity Test Mode tCT_Valid Max
TEN AC Input High Voltage (VIH(AC)_TEN) Min
TEN AC Input High Voltage (VIH(AC)_TEN) Max
TEN DC Input High Voltage (VIH(DC)_TEN) Min
TEN DC Input High Voltage (VIH(DC)_TEN) Max
TEN DC Input Low Voltage (VIL(DC)_TEN) Min
TEN DC Input Low Voltage (VIL(DC)_TEN) Max
TEN AC Input Low Voltage (VIL(AC)_TEN) Min
TEN AC Input Low Voltage (VIL(AC)_TEN) Max
TEN Input signal Falling time (TF_input_TEN) Max
TEN Input signal Rising time (TR_input_TEN) Max
RESET_n AC Input High Voltage (VIH(AC)_RESET) Min
RESET_n AC Input High Voltage (VIH(AC)_RESET) Max
RESET_n DC Input High Voltage (VIH(DC)_RESET) Min
RESET_n DC Input High Voltage (VIH(DC)_RESET) Max
RESET_n DC Input Low Voltage (VIL(DC)_RESET) Min
RESET_n DC Input Low Voltage (VIL(DC)_RESET) Max
RESET_n AC Input Low Voltage (VIL(AC)_RESET) Min
RESET_n AC Input Low Voltage (VIL(AC)_RESET) Max
RESET_n Rising time (TR_RESET) Max
RESET pulse width (tPW_RESET) Min
RON34Pd, VOLdc=0.5*VDDQ, Min
RON34Pd, VOLdc=0.5*VDDQ, Nom
RON34Pd, VOLdc=0.5*VDDQ, Max
RON34Pd, VOMdc=0.8*VDDQ, Min
RON34Pd, VOMdc=0.8*VDDQ, Nom
RON34Pd, VOMdc=0.8*VDDQ, Max
RON34Pd, VOHdc=0.95*VDDQ, Min
RON34Pd, VOHdc=0.95*VDDQ, Nom
RON34Pd, VOHdc=0.95*VDDQ, Max
RON34Pu, VOLdc=0.5*VDDQ, Min
RON34Pu, VOLdc=0.5*VDDQ, Nom
RON34Pu, VOLdc=0.5*VDDQ, Max
RON34Pu, VOMdc=0.8*VDDQ, Min
RON34Pu, VOMdc=0.8*VDDQ, Nom
RON34Pu, VOMdc=0.8*VDDQ, Max
RON34Pu, VOHdc=0.95*VDDQ, Min
RON34Pu, VOHdc=0.95*VDDQ, Nom
RON34Pu, VOHdc=0.95*VDDQ, Max
RON48Pd, VOLdc=0.5*VDDQ, Min
RON48Pd, VOLdc=0.5*VDDQ, Nom
RON48Pd, VOLdc=0.5*VDDQ, Max
RON48Pd, VOMdc=0.8*VDDQ, Min
RON48Pd, VOMdc=0.8*VDDQ, Nom
RON48Pd, VOMdc=0.8*VDDQ, Max
RON48Pd, VOHdc=0.95*VDDQ, Min
RON48Pd, VOHdc=0.95*VDDQ, Nom
RON48Pd, VOHdc=0.95*VDDQ, Max
RON48Pu, VOLdc=0.5*VDDQ, Min
RON48Pu, VOLdc=0.5*VDDQ, Nom
RON48Pu, VOLdc=0.5*VDDQ, Max
RON48Pu, VOMdc=0.8*VDDQ, Min
RON48Pu, VOMdc=0.8*VDDQ, Nom
RON48Pu, VOMdc=0.8*VDDQ, Max
RON48Pu, VOHdc=0.95*VDDQ, Min
RON48Pu, VOHdc=0.95*VDDQ, Nom
RON48Pu, VOHdc=0.95*VDDQ, Max
Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Min
Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte variation pull-up, MMPudd, VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte variation pull-dn, MMPddd, VOMdc=0.8*VDDQ, Max
Loopback RON34Pd, VOLdc=0.5*VDDQ, Min
Loopback RON34Pd, VOLdc=0.5*VDDQ, Nom
Loopback RON34Pd, VOLdc=0.5*VDDQ, Max
Loopback RON34Pd, VOMdc=0.8*VDDQ, Min
Loopback RON34Pd, VOMdc=0.8*VDDQ, Nom
Loopback RON34Pd, VOMdc=0.8*VDDQ, Max
Loopback RON34Pd, VOHdc=0.95*VDDQ, Min
Loopback RON34Pd, VOHdc=0.95*VDDQ, Nom
Loopback RON34Pd, VOHdc=0.95*VDDQ, Max
Loopback RON34Pu, VOLdc=0.5*VDDQ, Min
Loopback RON34Pu, VOLdc=0.5*VDDQ, Nom
Loopback RON34Pu, VOLdc=0.5*VDDQ, Max
Loopback RON34Pu, VOMdc=0.8*VDDQ, Min
Loopback RON34Pu, VOMdc=0.8*VDDQ, Nom
Loopback RON34Pu, VOMdc=0.8*VDDQ, Max
Loopback RON34Pu, VOHdc=0.95*VDDQ, Min
Loopback RON34Pu, VOHdc=0.95*VDDQ, Nom
Loopback RON34Pu, VOHdc=0.95*VDDQ, Max
Loopback Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Min
Loopback Mismatch between pull-up and pull-down, MMPuPd, VOMdc=0.8*VDDQ, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up, MMPudd, VOMdc=0.8*VDDQ, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn, MMPddd, VOMdc=0.8*VDDQ, Max
Loopback LBDQS Output Low Time, tLBQSL, MIN (DDR5-3200 to 4800)
Loopback LBDQS Output High Time, tLBQSH, MIN (DDR5-3200 to 4800)
Loopback LBDQS to LBDQ Skew, tLBDQSQ, MIN (DDR5-3200 to 4800)
Loopback LBDQ Output Time from LBDQS, tLBQH, MIN (DDR5-3200 to 4800)
Loopback Data valid window (tLBQH-tLBDQSQ) of each UI per DRAM, tLBDVW, MIN (DDR5-3200 to 4800)
Alert_n output RONPd, VOLdc=0.1*VDDQ, Min
Alert_n output RONPd, VOLdc=0.1*VDDQ, Max
Alert_n output RONPd, VOMdc=0.8*VDDQ, Min
Alert_n output RONPd, VOMdc=0.8*VDDQ, Max
Alert_n output RONPd, VOHdc=0.95*VDDQ, Min
Alert_n output RONPd, VOHdc=0.95*VDDQ, Max
CT Mode RONPu_CT, VOBdc=0.2xVDDQ, Max
CT Mode RONPu_CT, VOLdc=0.5xVDDQ, Max
CT Mode RONPu_CT, VOMdc=0.8xVDDQ, Max
CT Mode RONPu_CT, VOHdc=0.95xVDDQ, Max
Single-ended Output high measurement level VOH (for output SR), DDR5-3200-6400
Single-ended Output low measurement level VOL (for output SR), DDR5-3200-6400
Single-ended Output high measurement level VOH for Loopback Signals (for output SR), DDR5-3200-6400
Single-ended Output low measurement level VOL for Loopback Signals (for output SR), DDR5-3200-6400
Single-ended output slew rate, SRQse, MIN (DDR5-3200 to 4800)
Single-ended output slew rate, SRQse, MAX (DDR5-3200 to 4800)
Differential Output high measurement level VOHdiff (for output SR), DDR5-3200-6400
Differential Output low measurement level VOLdiff (for output SR), DDR5-3200-6400
Differential output slew rate, SRQdiff, MIN (DDR5-3200 to 4800)
Differential output slew rate, SRQdiff, MAX (DDR5-3200 to 4800)
Tx DQS Rj RMS Value of 1-UI Jitter without BUJ, tTx_DQS_1UI_Rj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQS Dj pp Value of 1-UI Jitter without BUJ, tTx_DQS_1UI_Dj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQS Rj RMS Value of N-UI jitter without BUJ (1<N<4), tTx_DQS_NUI_Rj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4), tTx_DQS_NUI_Dj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQ Rj RMS of 1-UI jitter without BUJ, tTx_DQ_1UI_Rj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQ Dj pp 1-UI jitter without BUJ, tTx_DQ_1UI_Dj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQ Rj RMS of N-UI jitter without BUJ (1<N<4), tTx_DQ_NUI_Rj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4), tTx_DQ_NUI_Dj_NoBUJ, MAX (DDR5-3200 to 4800)
Tx DQ Delay of any data lane relative to strobe lane, tTx_DQS2DQ, MIN (DDR5-3200 to 4800)
Tx DQ Delay of any data lane relative to strobe lane, tTx_DQS2DQ, MAX (DDR5-3200 to 4800)
Tx DQ Stressed Eye Height, 1UI skew, TxEH_DQ_SES_1UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Width, 1UI skew, TxEW_DQ_SES_1UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Height, 2UI skew, TxEH_DQ_SES_2UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Width, 2UI skew, TxEW_DQ_SES_2UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Height, 3UI skew, TxEH_DQ_SES_3UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Width, 3UI skew, TxEW_DQ_SES_3UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Height, 4UI skew, TxEH_DQ_SES_4UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Width, 4UI skew, TxEW_DQ_SES_4UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Height, 5UI skew, TxEH_DQ_SES_5UI, MIN (DDR5-3200 to 4800)
Tx DQ Stressed Eye Width, 5UI skew, TxEW_DQ_SES_5UI, MIN (DDR5-3200 to 4800)
Module configuration
Module Current measurement basis
Drawing title
General tolerance
Module overall width (Front)
Module width (Front)
Front contact span (left segment)
Front contact span (right segment)
Front edge offset
Front edge dimension
Registering Clock Driver height
Registering Clock Driver width
Module height (Back)
Side thickness
Detail A corner radius
Detail A dimension
Detail B contact depth
Detail B contact length
Detail B contact width
Detail B contact pitch
Detail B Pin 39
Detail B Pin 51
Detail B Pin 35
Detail B Pin 47
Detail C contact depth
Detail C contact length
Detail C contact width
Detail C contact pitch
Detail C Pin 122
Detail C Pin 110
Detail C Pin 105
Detail C Pin 117
Detail D contact width
Detail D non-metalized keep out area
Detail D max dimension
Detail D contact width (lower)
Detail D contact thickness
Detail D dimension
Detail D max dimension (second group)
Detail E contact width
Detail E dimension
Detail E contact length
Detail E contact dimension
Detail E/F contact dimension
Detail A/F contact width
Detail A/F contact thickness
Detail A/F dimension
Detail F Pin 1
Component: Registering Clock Driver
Component: SPD
Component: TS
Module Current measurement note
Module title
Dimensional tolerance note
Module overall length (outer)
Module length (inner)
Edge offset / left dimension
Contact field dimension (left)
Contact field dimension (right)
Left edge contact dimension
Right edge contact dimension
Module height (front)
PCB height to step (front)
Registering Clock Driver label
SPD label
TS (Temperature Sensor) label
PCB height (back)
Notch/keying dimension (back)
Side thickness (max)
Detail A reference
Detail B reference
Detail C reference
Detail D reference
Detail E reference
Detail F reference
Contacts A,F corner radius
Contacts A,F dimension
Contact width
Contact width tolerance
Contacts B dimension
Contacts C dimension
Contacts D contact width
Contacts D contact width tolerance
Contacts D dimension
Non-metalized keep out area note
Keep out dimension (max)
Detail E dimension (tolerance)
Detail of Contacts E dimension
Detail of Contacts E dimension (tolerance)
Disclaimer
Intended use
Bank configuration (x4/x8)
Bank configuration (x16)
Bank Group
Burst length support
Training mode
Absolute Maximum DC Rating - Voltage on VDD pin relative to Vss
Absolute Maximum DC Rating - Voltage on VDDQ pin relative to Vss
Absolute Maximum DC Rating - Voltage on VPP pin relative to Vss
Absolute Maximum DC Rating - Voltage on any pin relative to Vss
Absolute Maximum DC Rating - Storage Temperature
Recommended DC Operating Condition - Device Supply Voltage (VDD) Min.
Recommended DC Operating Condition - Device Supply Voltage (VDD) Typ.
Recommended DC Operating Condition - Device Supply Voltage (VDD) Max.
Recommended DC Operating Condition - VDD Z(f) Spec Freq: 2Mhz to 10Mhz Zmax
Recommended DC Operating Condition - VDD Z(f) Spec Freq: 20Mhz Zmax
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Min.
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Typ.
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Max.
Recommended DC Operating Condition - VDDQ Z(f) Spec Freq: 2Mhz to 10Mhz Zmax
Recommended DC Operating Condition - VDDQ Z(f) Spec Freq: 20Mhz Zmax
Recommended DC Operating Condition - Core Power Voltage (VPP) Min.
Recommended DC Operating Condition - Core Power Voltage (VPP) Typ.
Recommended DC Operating Condition - Core Power Voltage (VPP) Max.
Recommended DC Operating Condition - VPP Z(f) Spec Freq: 2Mhz to 10Mhz Zmax
Recommended DC Operating Condition - VPP Z(f) Spec Freq: 20Mhz Zmax
Table title
RON34Pd VOLdc=0.5*VDDQ
RON34Pd VOMdc=0.8*VDDQ
RON34Pd VOHdc=0.95*VDDQ
RON34Pu VOLdc=0.5*VDDQ
RON34Pu VOMdc=0.8*VDDQ
RON34Pu VOHdc=0.95*VDDQ
RON48Pd VOLdc=0.5*VDDQ
RON48Pd VOMdc=0.8*VDDQ
RON48Pd VOHdc=0.95*VDDQ
RON48Pu VOLdc=0.5*VDDQ
RON48Pu VOMdc=0.8*VDDQ
RON48Pu VOHdc=0.95*VDDQ
Mismatch between pull-up and pull-down, MMPuPd; VOMdc=0.8*VDDQ
Mismatch DQ-DQ within byte variation pull-up, MMPudd; VOMdc=0.8*VDDQ
Mismatch DQ-DQ within byte variation pull-dn, MMPddd; VOMdc=0.8*VDDQ
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
MMPuPd formula
MMPudd formula
MMPddd formula
Revision
Internal read command to first data (tAA)
ACT to internal read or write delay time (tRCD)
Row Precharge Time (tRP)
ACT to ACT or REF command period (tRC)
CAS Write Latency (CWL)
Supported Frequency Down Bin tAAmin
Down Bin 3200C
Down Bin 3200BN/3200B
Down Bin 3200AN
Down Bin 3600C
Down Bin 3600BN/3600B
Down Bin 3600AN
Down Bin 4000C
Down Bin 4000BN/4000B
Down Bin 4000AN
Down Bin 4400C
Down Bin 4400BN/4400B
Down Bin 4400AN
Supported CL (DDR5-4400)
Down Bin 4800C
Down Bin 4800BN
Down Bin 4800B
Down Bin 4800AN
Supported CL (DDR5-4800)
Module organization
Module Current note
Module Type (decoder, R)
Voltage on any pin relative to Vss (Absolute Maximum)
Storage Temperature (Absolute Maximum)
tREFI1 REFab Normal, 0°C <= TCASE <= 85°C (rREFI)
tREFI1 REFab Normal, 85°C < TCASE <= 95°C (rREFI/2)
tREFI2 REFab Fine Granularity, 0°C <= TCASE <= 85°C (rREFI/2)
tREFI2 REFab Fine Granularity, 85°C < TCASE <= 95°C (rREFI/4)
tREFIsb REFsb Fine Granularity, 0°C <= TCASE <= 85°C (rREFI/(2*n))
tREFIsb REFsb Fine Granularity, 85°C < TCASE <= 95°C (rREFI/(4*n))
Device Supply Voltage (Recommended DC) Min
Device Supply Voltage (Recommended DC) Typ
Device Supply Voltage (Recommended DC) Max
Device Supply Voltage Z(f) Spec 2MHz to 10MHz (Zmax)
Device Supply Voltage Z(f) Spec 20MHz (Zmax)
Supply Voltage for I/O (Recommended DC) Min
Supply Voltage for I/O (Recommended DC) Typ
Supply Voltage for I/O (Recommended DC) Max
Supply Voltage for I/O Z(f) Spec 2MHz to 10MHz (Zmax)
Supply Voltage for I/O Z(f) Spec 20MHz (Zmax)
Core Power Voltage (Recommended DC) Min
Core Power Voltage (Recommended DC) Typ
Core Power Voltage (Recommended DC) Max
Core Power Voltage Z(f) Spec 2MHz to 10MHz (Zmax)
Core Power Voltage Z(f) Spec 20MHz (Zmax)
VciVW Rx Mask voltage p-p Max (Table 1)
TcIVW Rx Timing Window Max (Table 1)
VIHL_AC CA Input Pulse Amplitude (Table 1)
TcIPW CA Input Pulse Width (Table 1)
SRIN_cIVW Input Slew Rate over VcIVW Min (Table 1)
SRIN_cIVW Input Slew Rate over VcIVW Max (Table 1)
tCK DRAM Reference clock frequency Min (Table 2)
tCK DRAM Reference clock frequency Max (Table 2)
tCK_Duty_UI_Error Duty Cycle Error Max (Table 2)
tCK_1UI_Rj_NoBUJ Rj RMS value of 1-UI Jitter Max (Table 2)
tCK_1UI_Dj_NoBUJ Dj pp value of 1-UI Jitter Max (Table 2)
tCK_1UI_Tj_NoBUJ Tj value of 1-UI Jitter Max (Table 2)
tCK_NUI_Rj_NoBUJ Rj RMS value of N-UI Jitter (N=2,3) Max (Table 2)
tCK_NUI_Dj_NoBUJ Dj pp value of N-UI Jitter (N=2,3) Max (Table 2)
tCK_NUI_Tj_NoBUJ Tj value of N-UI Jitter (N=2,3) Max (Table 2)
tCK_NUI_Rj_NoBUJ Rj RMS value of N-UI Jitter (N=4,5,6,...,30) Max (Table 2)
tCK_NUI_Dj_NoBUJ Dj pp value of N-UI Jitter (N=4,5,6,...,30) Max (Table 2)
tCK_NUI_Tj_NoBUJ Tj value of N-UI Jitter (N=4,5,6,...,30) Max (Table 2)
VIX_CK_Ratio Clock differential input crosspoint voltage ratio Max (Table 3)
VRx_CK Input Clock Voltage Sensitivity (differential pp) Max (Table 4)
TxEH_DQ_SES_1UI - Eye Height (skew DQ/DQS 1UI), Min
VIHdiffCK Differential input high measurement level (CK_t, CK_c) (Table 5)
VILdiffCK Differential input low measurement level (CK_t, CK_c) (Table 5)
SRIdiff_CK Differential Input Slew Rate for CK_t, CK_c Min (Table 7)
SRIdiff_CK Differential Input Slew Rate for CK_t, CK_c Max (Table 7)
tRx_DQ_tMargin DQ Timing Width Min (Table 8)
ΔtRx_DQ_tMargin_DQS_DCD Degradation of timing width with DCD injection in DQS Max (Table 8)
ΔtRx_DQ_tMargin_DQS_Rj Degradation of timing width with Rj injection in DQS Max (Table 8)
ΔtRx_DQ_tMargin_DQS_DCD_Rj Degradation of timing width with both DCD and Rj injection in DQS Max (Table 8)
tRx_DQS2DQ Delay of any data lane relative to DQS_t/DQS_c crossing Min (Table 8)
tRx_DQS2DQ Delay of any data lane relative to DQS_t/DQS_c crossing Max (Table 8)
tRx_DQS_DCD Applied DCD to the DQS Max (Table 9)
tRx_DQS_Rj Applied Rj RMS to the DQS Max (Table 9)
tRx_DQS_DCD_Rj Applied DCD and Rj RMS to the DQS Max (Table 9)
VRx_DQS DQS Rx Input Voltage Sensitivity (differential pp) Max (Table 10)
VIX_DQS_Ratio DQS differential input crosspoint voltage ratio Max (Table 11)
VIHdiffDQS Differential input high measurement level (DQS_t, DQS_c) (Table 12)
VILdiffDQS Differential input low measurement level (DQS_t, DQS_c) (Table 12)
SRIdiff_DQS Differential Input Slew Rate for DQS_t, DQS_c Min (Table 14)
SRIdiff_DQS Differential Input Slew Rate for DQS_t, DQS_c Max (Table 14)
VRx_DQ Minimum DQ Rx input voltage sensitivity applied around Vref Max (Table 15)
RxEH_Stressed_Eye_Golden_Ref_Channel_1 Eye height of stressed eye Max (Table 16)
RxEW_Stressed_Eye_Golden_Ref_Channel_1 Eye width of stressed eye Max (Table 16)
Vswing_Stressed_Eye_Golden_Ref_Channel_1 Vswing stress to meet above data eye Max (Table 16)
Sj_Stressed_Eye_Golden_Ref_Channel_1 Injected sinusoidal jitter at 200 MHz Min (Table 16)
Sj_Stressed_Eye_Golden_Ref_Channel_1 Injected sinusoidal jitter at 200 MHz Max (Table 16)
Rj_Stressed_Eye_Golden_Ref_Channel_1 Injected Random wide band (10 MHz-1 GHz) Jitter Min (Table 16)
Rj_Stressed_Eye_Golden_Ref_Channel_1 Injected Random wide band (10 MHz-1 GHz) Jitter Max (Table 16)
Vnoise_Stressed_Eye_Golden_Ref_Channel_1 Injected voltage noise (PRBS23 / 2.1 GHz) Min (Table 16)
Vnoise_Stressed_Eye_Golden_Ref_Channel_1 Injected voltage noise (PRBS23 / 2.1 GHz) Max (Table 16)
Golden_Ref_Channel_1_Characteristics (Table 16)
tCT_IS AC parameter for Connectivity Test (CT) Mode Min (Table 17)
tCT_IS AC parameter for Connectivity Test (CT) Mode Max (Table 17)
tCT_Enable AC parameter for Connectivity Test (CT) Mode Min (Table 17)
tCT_Enable AC parameter for Connectivity Test (CT) Mode Max (Table 17)
tCT_Valid AC parameter for Connectivity Test (CT) Mode Min (Table 17)
tCT_Valid AC parameter for Connectivity Test (CT) Mode Max (Table 17)
VIH(AC)_TEN TEN AC Input High Voltage Min (Table 18)
VIH(AC)_TEN TEN AC Input High Voltage Max (Table 18)
VIH(DC)_TEN TEN DC Input High Voltage Min (Table 18)
VIH(DC)_TEN TEN DC Input High Voltage Max (Table 18)
VIL(DC)_TEN TEN DC Input Low Voltage Min (Table 18)
VIL(DC)_TEN TEN DC Input Low Voltage Max (Table 18)
VIL(AC)_TEN TEN AC Input Low Voltage Min (Table 18)
VIL(AC)_TEN TEN AC Input Low Voltage Max (Table 18)
TF_input_TEN TEN Input signal Falling time Max (Table 18)
TR_input_TEN TEN Input signal Rising time Max (Table 18)
VIH(AC)_RESET AC Input High Voltage Min (Table 19)
VIH(AC)_RESET AC Input High Voltage Max (Table 19)
VIH(DC)_RESET DC Input High Voltage Min (Table 19)
VIH(DC)_RESET DC Input High Voltage Max (Table 19)
VIL(DC)_RESET DC Input Low Voltage Min (Table 19)
VIL(DC)_RESET DC Input Low Voltage Max (Table 19)
VIL(AC)_RESET AC Input Low Voltage Min (Table 19)
VIL(AC)_RESET AC Input Low Voltage Max (Table 19)
TR_RESET Rising time Max (Table 19)
tPW_RESET RESET pulse width Min (Table 19)
Connectivity Test Mode input level - TEN pin
Connectivity Test Mode input level - CS_n
Connectivity Test Mode input level - RESET_n
RON34Pd @ VOLdc=0.5*VDDQ, Min
RON34Pd @ VOLdc=0.5*VDDQ, Nom
RON34Pd @ VOLdc=0.5*VDDQ, Max
RON34Pd @ VOMdc=0.8*VDDQ, Min
RON34Pd @ VOMdc=0.8*VDDQ, Max
RON34Pd @ VOHdc=0.95*VDDQ, Min
RON34Pd @ VOHdc=0.95*VDDQ, Max
RON34Pu @ VOLdc=0.5*VDDQ, Min
RON34Pu @ VOLdc=0.5*VDDQ, Max
RON48Pd @ VOLdc=0.5*VDDQ, Min
RON48Pd @ VOLdc=0.5*VDDQ, Max
RON48Pu @ VOLdc=0.5*VDDQ, Min
RON48Pu @ VOLdc=0.5*VDDQ, Max
Mismatch pull-up/pull-down MMPuPd @ VOMdc=0.8*VDDQ, Min
Mismatch pull-up/pull-down MMPuPd @ VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte pull-up MMPudd, Max
Mismatch DQ-DQ within byte pull-dn MMPddd, Max
Loopback RON34Pd @ VOLdc=0.5*VDDQ, Min
Loopback RON34Pd @ VOLdc=0.5*VDDQ, Max
Loopback Mismatch MMPuPd, Min
Loopback Mismatch MMPuPd, Max
Loopback LBDQS Output Low Time tLBQSL, Min
Loopback LBDQS Output High Time tLBQSH, Min
Loopback LBDQS to LBDQ Skew tLBDQSQ, Min
Loopback LBDQ Output Time from LBDQS tLBQH, Min
Loopback Data valid window tLBDVW, Min
Alert_n RONPd @ VOLdc=0.1*VDDQ, Min
Alert_n RONPd @ VOLdc=0.1*VDDQ, Max
Alert_n RONPd @ VOMdc=0.8*VDDQ, Min
Alert_n RONPd @ VOHdc=0.95*VDDQ, Max
CT mode RONPd_CT @ VOBdc=0.2*VDDQ, Max
CT mode RONPd_CT @ VOLdc=0.5*VDDQ, Max
CT mode RONPd_CT @ VOMdc=0.8*VDDQ, Max
CT mode RONPd_CT @ VOHdc=0.95*VDDQ, Max
CT mode uncalibrated drive strength tolerance
VOH output high measurement level (for output SR)
VOL output low measurement level (for output SR)
Single ended output slew rate SRQse, Min
Single ended output slew rate SRQse, Max
VOHdiff differential output high measurement level
VOLdiff differential output low measurement level
Differential output slew rate SRQdiff, Min
Differential output slew rate SRQdiff, Max
Tx DQS Rj RMS 1-UI jitter without BUJ, Max
Tx DQS Dj pp 1-UI jitter without BUJ, Max
Tx DQS Dj pp N-UI jitter without BUJ (1<N<4), Max
Tx DQS Rj max value note
Tx DQ Dj pp 1-UI jitter without BUJ, Max
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4), Max
Tx DQS2DQ delay of any data lane relative to strobe lane, Min
Tx DQS2DQ delay of any data lane relative to strobe lane, Max
TxEW_DQ_SES_1UI Eye Width at 1UI skew, Min
TxEW_DQ_SES_2UI Eye Width at 2UI skew, Min
TxEW_DQ_SES_3UI Eye Width at 3UI skew, Min
TxEH_DQ_SES Eye Height at transmitter
Tx DQ Stressed Eye BER / confidence level
DDR5-4400B CL-nRCD-nRP
DDR5-4400B tAA internal read command to first data
DDR5-4400B tRCD ACT to internal read or write delay
DDR5-4400B tRP row precharge time
DDR5-4400B tRAS ACT to PRE command period, min
DDR5-4400B tRC ACT to ACT or REF command period
DDR5-4400B CWL CAS write latency
DDR5-4400 Supported CL
DDR5-4400B tCK(AVG) min @ CL=36 CWL=34
DDR5-4800B CL-nRCD-nRP
DDR5-4800B tAA internal read command to first data
DDR5-4800B tRCD ACT to internal read or write delay
DDR5-4800B tRP row precharge time
DDR5-4800B tRC ACT to ACT or REF command period
DDR5-4800B CWL CAS write latency
DDR5-4800B tCK(AVG) min @ CL=40 CWL=38
DDR5-4800 Supported CL
Specification type
Note
Die basis
Document date
Description
Training Mode
CA0_A - CA6_A
CA0_B - CA6_B
CS0_A_n - CS1_A_n
CS0_B_n - CS1_B_n
DQ0_A - DQ31_A
DQ0_B - DQ31_B
CB0_A - CB7_A
CB0_B - CB7_B
TDQS0_A_t-TDQS9_A_t
PAR_A
PAR_B
RSP_A_n
VIN_BULK
VSS
VIN_MGMT
PWR_GOOD / FAIL_n
SCL
ALERT_n
SDA
RESET_n
SAA
LBD
CK_t
LBS
CK_c
RFU
CK_t, CK_c
CA0_A - CA6_A, CA0_B - CA6_B
CS0_A_n - CS1_A_n, CS0_B_n - CS1_B_n
DQ0_A - DQ31_A, DQ0_B - DQ31_B
DQS0_A_t - DQS9_A_t (data strobe)
DM0_A_n-DM3_A_n, DM0_B_n-DM3_B_n
Pin 1
Pin 147 (back side, KEY adjacent)
Pin 288
Block diagram title
Register command/address input
Register chip select input
Register parity input
Register clock true input
Register clock complement input
Register reset input
Register loopback data input
Register loopback strobe input
Register alert input
Register block label
Register output A command/address
Register output A chip select
Register output A clock
Register output A reset
Register output A derror in
Register output A DLBD
Register output A DLBS
Register output B command/address
Register output B chip select
Register output B clock
Register output B reset
Register output B derror in
Register output B DLBD
Register output B DLBS
DRAM device placement (front, channel A row)
DRAM device placement (back, channel B row)
Resistor value note
DRAM devices (top module section)
Command/address bus (top section)
Data strobe / data byte mapping (top section)
DRAM devices (bottom module section)
Command/address bus (bottom section)
Data strobe / data byte mapping (bottom section)
DRAM ZQ pin resistor note
VDD - Voltage on VDD pin relative to Vss
VDDQ - Voltage on VDDQ pin relative to Vss
VPP - Voltage on VPP pin relative to Vss
VIN, VOUT - Voltage on any pin relative to Vss
TSTG - Storage Temperature
tREFI1 REFab Normal (0C<=TCASE<=85C)
tREFI1 REFab Normal (85C<TCASE<=95C)
tREFI2 REFab Fine Granularity (0C<=TCASE<=85C)
tREFI2 REFab Fine Granularity (85C<TCASE<=95C)
tREFIsb REFsb Fine Granularity (0C<=TCASE<=85C)
tREFIsb REFsb Fine Granularity (85C<TCASE<=95C)
VDD Device Supply Voltage - Min
VDD Device Supply Voltage - Typ
VDD Device Supply Voltage - Max
VDD Z(f) Spec 2MHz to 10MHz Zmax
VDD Z(f) Spec 20MHz Zmax
VDDQ Supply Voltage for I/O - Min
VDDQ Supply Voltage for I/O - Typ
VDDQ Supply Voltage for I/O - Max
VDDQ Z(f) Spec 2MHz to 10MHz Zmax
VDDQ Z(f) Spec 20MHz Zmax
VPP Core Power Voltage - Min
VPP Core Power Voltage - Typ
VPP Core Power Voltage - Max
VPP Z(f) Spec 2MHz to 10MHz Zmax
VPP Z(f) Spec 20MHz Zmax
Rx Mask voltage - p-p (VciVW) - Max
Rx Timing Window (TcIVW) - Max
CA Input Pulse Amplitude (VIHL_AC)
CA Input Pulse Width (TcIPW)
Input Slew Rate over VcIVW (SRIN_cIVW) - Min
Input Slew Rate over VcIVW (SRIN_cIVW) - Max
DRAM Reference clock frequency (tCK) - Min
DRAM Reference clock frequency (tCK) - Max
Duty Cycle Error (tCK_Duty_UI_Error) - Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - Max
Rj RMS value of N-UI Jitter N=2,3 (tCK_NUI_Rj_NoBUJ) - Max
Dj pp value of N-UI Jitter N=2,3 (tCK_NUI_Dj_NoBUJ) - Max
Tj value of N-UI Jitter N=2,3 (tCK_NUI_Tj_NoBUJ) - Max
Rj RMS value of N-UI Jitter N=4..30 (tCK_NUI_Rj_NoBUJ) - Max
Dj pp value of N-UI Jitter N=4..30 (tCK_NUI_Dj_NoBUJ) - Max
Tj value of N-UI Jitter N=4..30 (tCK_NUI_Tj_NoBUJ) - Max
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - Max (DDR5-3200-4800)
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - Max (DDR5-6800-8400)
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - Max
VIHdiffCK Differential input high measurement level (CK_t, CK_c)
VILdiffCK Differential input low measurement level (CK_t, CK_c)
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - Max
DQ Timing Width (tRx_DQ_tMargin) - Min
Degradation of timing width with DCD injection in DQS (tRx_DQ_tMargin_DQS_DCD) - Max
Degradation of timing width with Rj injection in DQS (tRx_DQ_tMargin_DQS_Rj) - Max
Degradation of timing width with both DCD and Rj injection in DQS (tRx_DQ_tMargin_DQS_DCD_Rj) - Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - Max
Applied DCD to the DQS (tRx_DQS_DCD) - Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) - Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - Max
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) - Max (DDR5-3200-4800)
VIHdiffDQS Differential input high measurement level (DQS_t, DQS_c)
VILdiffDQS Differential input low measurement level (DQS_t, DQS_c)
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - Max
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - Max
Eye height of stressed eye Golden Ref Channel 1 (RxEH) - Max
Eye width of stressed eye Golden Ref Channel 1 (RxEW) - Max
Vswing stress to meet above data eye (Vswing) - Max
Injected sinusoidal jitter at 200 MHz (Sj) - Min
Injected sinusoidal jitter at 200 MHz (Sj) - Max
Injected Random wide band (10MHz-1GHz) Jitter (Rj) - Min
Injected Random wide band (10MHz-1GHz) Jitter (Rj) - Max
Injected voltage noise PRBS23 or 2.1 GHz (Vnoise) - Min
Injected voltage noise PRBS23 or 2.1 GHz (Vnoise) - Max
Golden Reference Channel 1 Characteristics
tCT_IS - Min
tCT_Enable - Min
tCT_Valid - Max
TEN AC Input High Voltage (VIH(AC)_TEN) - Min
TEN AC Input High Voltage (VIH(AC)_TEN) - Max
IDD6N current definition
IDD6E current definition
IDD7 current definition
IDD8 current definition
IDD9 (Optional) current definition
Module Density
Module current note
Module overall length (Front)
Module length dimension (Front)
Front edge offset dimension
Notch/feature dimension (Front)
Edge dimension (Front)
Contact area length left (Front)
Contact area length right (Front)
Module overall length (Back)
Module length dimension (Back)
Back vertical dimension
SPD component label
TS component label
Contact pitch (Side)
Side max dimension
Detail A radius
Detail A Pin 1
Detail A Pin 35
Detail A Pin 47
Detail A Pin 105
Detail A Pin 117
Detail of Contacts A,F dimension
Detail of Contacts B dimension
Detail of Contacts B Pin 39
Detail of Contacts B Pin 51
Detail of Contacts C dimension
Detail of Contacts C Pin 122
Detail of Contacts C Pin 110
Detail of Contacts D dimension
Non-metalized keep out area note (B)
Keep out area max (B)
Non-metalized keep out area note (D)
Keep out area max (D)
Detail F dimension
Table
Date
Bank (x4/x8)
Bank (x16)
Burst Length
Register input signal
Register output signal (A side)
Register output signal (B side)
DRAM placement designator (front, A side daisy-chain)
DRAM placement designator (back, A/B side daisy-chain)
Note 1 (resistor values)
DRAM placement designator (A-side group, top)
Command/address bus to A-side DRAMs
Data/strobe signal (A-side DRAM)
DRAM placement designator (B-side group, bottom)
Command/address bus to B-side DRAMs
Data/strobe signal (B-side DRAM)
Note 2 (DRAM ZQ pin resistor)
tREFI1 REFab Normal, 0°C<=TCASE<=85°C
tREFI1 REFab Normal, 85°C<TCASE<=95°C
tREFI2 REFab Fine Granularity, 0°C<=TCASE<=85°C
tREFI2 REFab Fine Granularity, 85°C<TCASE<=95°C
tREFIsb REFsb Fine Granularity, 0°C<=TCASE<=85°C
tREFIsb REFsb Fine Granularity, 85°C<TCASE<=95°C
Device Supply Voltage VDD (Recommended DC Operating)
VDD Z(f) Spec Freq 2MHz to 10MHz (Zmax)
VDD Z(f) Spec Freq 20MHz (Zmax)
Supply Voltage for I/O VDDQ (Recommended DC Operating)
VDDQ Z(f) Spec Freq 2MHz to 10MHz (Zmax)
VDDQ Z(f) Spec Freq 20MHz (Zmax)
Core Power Voltage VPP (Recommended DC Operating)
VPP Z(f) Spec Freq 2MHz to 10MHz (Zmax)
VPP Z(f) Spec Freq 20MHz (Zmax)
Rx Mask voltage p-p (VciVW) DDR5-3200 (Max)
Rx Mask voltage p-p (VciVW) DDR5-3600 (Max)
Rx Mask voltage p-p (VciVW) DDR5-4000 (Max)
Rx Mask voltage p-p (VciVW) DDR5-4400 (Max)
Rx Mask voltage p-p (VciVW) DDR5-4800 (Max)
Rx Timing Window (TcIVW) DDR5-3200 to 4800 (Max)
CA Input Pulse Amplitude (VIHL_AC) DDR5-3200 to 4000
CA Input Pulse Amplitude (VIHL_AC) DDR5-4400 to 4800
CA Input Pulse Width (TcIPW) DDR5-3200 to 4800
Input Slew Rate over VcIVW (SRIN_cIVW) DDR5-3200 to 4800 (Min)
Input Slew Rate over VcIVW (SRIN_cIVW) DDR5-3200 to 4800 (Max)
DRAM Reference clock frequency (tCK) DDR5-3200..4800 (Min)
DRAM Reference clock frequency (tCK) DDR5-3200..4800 (Max)
Duty Cycle Error (tCK_Duty_UI_Error) DDR5-3200..4400 (Max)
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) DDR5-3200..4800 (Max)
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) DDR5-3200..4800 (Max)
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) DDR5-3200..4800 (Max)
Rj RMS value of N-UI Jitter, N=2,3 (tCK_NUI_Rj_NoBUJ) DDR5-3200..4800 (Max)
Dj pp value of N-UI Jitter, N=2,3 (tCK_NUI_Dj_NoBUJ) DDR5-3200..4800 (Max)
Tj value of N-UI Jitter, N=2,3 (tCK_NUI_Tj_NoBUJ) DDR5-3200..4800 (Max)
Rj RMS value of N-UI Jitter, N=4..30 (tCK_NUI_Rj_NoBUJ) DDR5-3200..4800 (Max)
Dj pp value of N-UI Jitter, N=4..30 (tCK_NUI_Dj_NoBUJ) DDR5-3200..4800 (Max)
Tj value of N-UI Jitter, N=4..30 (tCK_NUI_Tj_NoBUJ) DDR5-3200..4800 (Max)
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) DDR5-3200..4800 (Max)
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) DDR5-6800..8400 (Max)
Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-3200 (Max)
Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-3600 (Max)
Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-4000 (Max)
Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-4400 (Max)
Input Clock Voltage Sensitivity (differential pp) VRx_CK DDR5-4800 (Max)
Differential input high measurement level CK (VIHdiffCK) DDR5-3200..6400
Differential input low measurement level CK (VILdiffCK) DDR5-3200..6400
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) DDR5-3200..4800 (Min)
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) DDR5-3200..4800 (Max)
DQ Timing Width (tRx_DQ_tMargin) DDR5-3200 (Min)
DQ Timing Width (tRx_DQ_tMargin) DDR5-3600 (Min)
DQ Timing Width (tRx_DQ_tMargin) DDR5-4000 (Min)
DQ Timing Width (tRx_DQ_tMargin) DDR5-4400 (Min)
DQ Timing Width (tRx_DQ_tMargin) DDR5-4800 (Min)
Degradation of timing width with DCD injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD) DDR5-3200..4800 (Max)
Degradation of timing width with Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_Rj) DDR5-3200..4800 (Max)
Degradation of timing width with both DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) DDR5-3200..4800 (Max)
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-3200..4000 (Min)
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-3200 (Max)
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-3600 (Max)
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-4000 (Max)
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-4400 (Max)
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) DDR5-4800 (Max)
Applied DCD to the DQS (tRx_DQS_DCD) DDR5-3200..4800 (Max)
Applied Rj RMS to the DQS (tRx_DQS_Rj) DDR5-3200..4800 (Max)
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) DDR5-3200..4800 (Max)
DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-3200 (Max)
DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-3600 (Max)
DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-4000 (Max)
DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-4400 (Max)
DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS DDR5-4800 (Max)
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) DDR5-3200..4800 (Max)
Differential input high measurement level DQS (VIHdiffDQS) DDR5-3200..6400
Differential input low measurement level DQS (VILdiffDQS) DDR5-3200..6400
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) DDR5-3200..4800
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-3200 (Max)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-3600 (Max)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-4000 (Max)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) DDR5-4400-6400 (Max)
Eye height of stressed eye for Golden Reference Channel 1 DDR5-3200 (Max)
Eye height of stressed eye for Golden Reference Channel 1 DDR5-3600 (Max)
Eye height of stressed eye for Golden Reference Channel 1 DDR5-4000 (Max)
Eye height of stressed eye for Golden Reference Channel 1 DDR5-4400 (Max)
Eye height of stressed eye for Golden Reference Channel 1 DDR5-4800 (Max)
Eye width of stressed eye Golden Reference Channel 1 DDR5-3200..4800 (Max)
Vswing stress to meet above data eye DDR5-3200..4800 (Max)
Injected sinusoidal jitter at 200 MHz to meet above data eye DDR5-3200..4800 (Min)
Injected sinusoidal jitter at 200 MHz to meet above data eye DDR5-3200..4800 (Max)
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye DDR5-3200..4800 (Min)
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye DDR5-3200..4800 (Max)
Injected voltage noise (PRBS23 / at 2.1 GHz) to meet above data eye DDR5-3200..4800 (Min)
Injected voltage noise (PRBS23 / at 2.1 GHz) to meet above data eye DDR5-3200..4800 (Max)
Golden Reference Channel 1 Characteristics DDR5-3200..4800
DFE tap range limit
Minimum BER requirement for stressed eye
Connectivity Test Mode tCT_IS (Min)
Connectivity Test Mode tCT_Enable (Min)
Connectivity Test Mode tCT_Valid (Max)
TEN AC Input High Voltage (VIH(AC)_TEN) (Min)
TEN AC Input High Voltage (VIH(AC)_TEN) (Max)
TEN DC Input High Voltage (VIH(DC)_TEN) (Min)
TEN DC Input High Voltage (VIH(DC)_TEN) (Max)
TEN DC Input Low Voltage (VIL(DC)_TEN) (Min)
TEN DC Input Low Voltage (VIL(DC)_TEN) (Max)
TEN AC Input Low Voltage (VIL(AC)_TEN) (Min)
TEN AC Input Low Voltage (VIL(AC)_TEN) (Max)
TEN Input signal Falling time (TF_input_TEN) (Max)
TEN Input signal Rising time (TR_input_TEN) (Max)
RESET_n AC Input High Voltage (VIH(AC)_RESET) (Min)
RESET_n AC Input High Voltage (VIH(AC)_RESET) (Max)
RESET_n DC Input High Voltage (VIH(DC)_RESET) (Min)
RESET_n DC Input High Voltage (VIH(DC)_RESET) (Max)
RESET_n DC Input Low Voltage (VIL(DC)_RESET) (Min)
RESET_n DC Input Low Voltage (VIL(DC)_RESET) (Max)
RESET_n AC Input Low Voltage (VIL(AC)_RESET) (Min)
RESET_n AC Input Low Voltage (VIL(AC)_RESET) (Max)
RESET_n Rising time (TR_RESET) (Max)
RESET pulse width (tPW_RESET) (Min)
Table 20 assumptions
RON34Pd Min @ VOLdc=0.5*VDDQ
RON34Pd Nom @ VOLdc=0.5*VDDQ
RON34Pd Max @ VOLdc=0.5*VDDQ
RON34Pd Min @ VOMdc=0.8*VDDQ
RON34Pd Nom @ VOMdc=0.8*VDDQ
RON34Pd Max @ VOMdc=0.8*VDDQ
RON34Pd Min @ VOHdc=0.95*VDDQ
RON34Pd Nom @ VOHdc=0.95*VDDQ
RON34Pd Max @ VOHdc=0.95*VDDQ
RON34Pu Min @ VOLdc=0.5*VDDQ
RON34Pu Nom @ VOLdc=0.5*VDDQ
RON34Pu Max @ VOLdc=0.5*VDDQ
RON34Pu Min @ VOMdc=0.8*VDDQ
RON34Pu Nom @ VOMdc=0.8*VDDQ
RON34Pu Max @ VOMdc=0.8*VDDQ
RON34Pu Min @ VOHdc=0.95*VDDQ
RON34Pu Nom @ VOHdc=0.95*VDDQ
RON34Pu Max @ VOHdc=0.95*VDDQ
RON48Pd Min @ VOLdc=0.5*VDDQ
RON48Pd Nom @ VOLdc=0.5*VDDQ
RON48Pd Max @ VOLdc=0.5*VDDQ
RON48Pd Min @ VOMdc=0.8*VDDQ
RON48Pd Nom @ VOMdc=0.8*VDDQ
RON48Pd Max @ VOMdc=0.8*VDDQ
RON48Pd Min @ VOHdc=0.95*VDDQ
RON48Pd Nom @ VOHdc=0.95*VDDQ
RON48Pd Max @ VOHdc=0.95*VDDQ
RON48Pu Min @ VOLdc=0.5*VDDQ
RON48Pu Nom @ VOLdc=0.5*VDDQ
RON48Pu Max @ VOLdc=0.5*VDDQ
RON48Pu Min @ VOMdc=0.8*VDDQ
RON48Pu Nom @ VOMdc=0.8*VDDQ
RON48Pu Max @ VOMdc=0.8*VDDQ
RON48Pu Min @ VOHdc=0.95*VDDQ
RON48Pu Nom @ VOHdc=0.95*VDDQ
RON48Pu Max @ VOHdc=0.95*VDDQ
Mismatch pull-up/pull-down MMPuPd Min @ VOMdc=0.8*VDDQ
Mismatch pull-up/pull-down MMPuPd Max @ VOMdc=0.8*VDDQ
Mismatch DQ-DQ within byte pull-up MMPudd Max @ VOMdc=0.8*VDDQ
Mismatch DQ-DQ within byte pull-dn MMPddd Max @ VOMdc=0.8*VDDQ
Loopback driver supported impedance
LB RON34Pd Min @ VOLdc=0.5*VDDQ
LB RON34Pd Nom @ VOLdc=0.5*VDDQ
LB RON34Pd Max @ VOLdc=0.5*VDDQ
LB RON34Pd Min @ VOMdc=0.8*VDDQ
LB RON34Pd Nom @ VOMdc=0.8*VDDQ
LB RON34Pd Max @ VOMdc=0.8*VDDQ
LB RON34Pd Min @ VOHdc=0.95*VDDQ
LB RON34Pd Nom @ VOHdc=0.95*VDDQ
LB RON34Pd Max @ VOHdc=0.95*VDDQ
LB RON34Pu Min @ VOLdc=0.5*VDDQ
LB RON34Pu Nom @ VOLdc=0.5*VDDQ
LB RON34Pu Max @ VOLdc=0.5*VDDQ
LB RON34Pu Min @ VOMdc=0.8*VDDQ
LB RON34Pu Nom @ VOMdc=0.8*VDDQ
LB RON34Pu Max @ VOMdc=0.8*VDDQ
LB RON34Pu Min @ VOHdc=0.95*VDDQ
LB RON34Pu Nom @ VOHdc=0.95*VDDQ
LB RON34Pu Max @ VOHdc=0.95*VDDQ
LB Mismatch pull-up/pull-down MMPuPd Min @ VOMdc=0.8*VDDQ
LB Mismatch pull-up/pull-down MMPuPd Max @ VOMdc=0.8*VDDQ
LB Mismatch LBDQS-LBDQ within device pull-up MMPudd Max
LB Mismatch LBDQS-LBDQ within device pull-dn MMPddd Max
Alert_n RONPd Min @ VOLdc=0.1*VDDQ
Alert_n RONPd Max @ VOLdc=0.1*VDDQ
Alert_n RONPd Min @ VOMdc=0.8*VDDQ
Alert_n RONPd Max @ VOMdc=0.8*VDDQ
Alert_n RONPd Min @ VOHdc=0.95*VDDQ
Alert_n RONPd Max @ VOHdc=0.95*VDDQ
CT RONPd_CT Max @ VOBdc=0.2xVDDQ
CT RONPd_CT Max @ VOLdc=0.5xVDDQ
CT RONPd_CT Max @ VOMdc=0.8xVDDQ
CT RONPd_CT Max @ VOHdc=0.95xVDDQ
CT RONPu_CT Max @ VOBdc=0.2xVDDQ
CT RONPu_CT Max @ VOLdc=0.5xVDDQ
CT RONPu_CT Max @ VOMdc=0.8xVDDQ
CT RONPu_CT Max @ VOHdc=0.95xVDDQ
VOH Output high measurement level (Loopback, for output SR)
VOL Output low measurement level (Loopback, for output SR)
tTx_DQS_1UI_Rj_NoBUJ Max (Rj RMS 1-UI without BUJ)
tTx_DQS_1UI_Dj_NoBUJ Max (Dj pp 1-UI without BUJ)
tTx_DQS_NUI_Rj_NoBUJ Max (Rj RMS N-UI without BUJ, 1<N<4)
tTx_DQS_NUI_Dj_NoBUJ Max (Dj pp N-UI without BUJ, 1<N<4)
Tx DQS Rj max alt value note
tTx_DQ_1UI_Rj_NoBUJ Max (Rj RMS 1-UI without BUJ)
tTx_DQ_1UI_Dj_NoBUJ Max (Dj pp 1-UI without BUJ)
tTx_DQ_NUI_Rj_NoBUJ Max (Rj RMS N-UI without BUJ, 1<N<4)
tTx_DQ_NUI_Dj_NoBUJ Max (Dj pp N-UI without BUJ, 1<N<4)
Tx DQ Rj max alt value note
TxEH_DQ_SES_1UI Eye Height @ DQ-DQS skew 1UI Min
TxEW_DQ_SES_1UI Eye Width @ DQ-DQS skew 1UI Min
TxEH_DQ_SES_2UI Eye Height @ DQ-DQS skew 2UI Min
TxEW_DQ_SES_2UI Eye Width @ DQ-DQS skew 2UI Min
TxEH_DQ_SES_3UI Eye Height @ DQ-DQS skew 3UI Min
TxEW_DQ_SES_3UI Eye Width @ DQ-DQS skew 3UI Min
TxEH_DQ_SES_4UI Eye Height @ DQ-DQS skew 4UI Min
TxEW_DQ_SES_4UI Eye Width @ DQ-DQS skew 4UI Min
TxEH_DQ_SES_5UI Eye Height @ DQ-DQS skew 5UI Min
TxEW_DQ_SES_5UI Eye Width @ DQ-DQS skew 5UI Min
Tx DQ Stressed Eye BER/Confidence condition
Section title
Front - overall width (outer)
Front - overall width (inner)
Front - dimension
Front - corner radius
Front - component label
Detail callout label
Back - dimension (vertical)
Back - dimension
Side - thickness
Detail of Contacts A,F - dimension
Detail of Contacts A,F - keep out area note
Detail of Contacts B - pin
Detail of Contacts C - pin
Detail of Contacts D - keep out area note
Detail E - pin
Page number
Base die
Notice
Temperature Encoding
Same Bank Refresh
VrefDQ / VrefCA / VrefCS Training
Post Package Repair
Input Clock Frequency Change
Maximum Power Saving Mode (MPSM)
Multi-Purpose Command (MPC)
Per DRAM Addressability (PDA)
Read Training Mode
CA Training Mode
CS Training Mode
Per Pin VREFDQ Training
Write Leveling Training Mode
Connectivity Test (CT)
ZQ Calibration
DFE for DQ
DQS Interval Oscillator
1N / 2N Mode support for Commands
ECC Transparency and Error Scrub
CRC (Cyclic Redundancy Check)
Loopback
Package Output Driver Test Mode
Training Modes
TDQS0_B_t-TDQS9_B_t
TDQS0_A_c-TDQS9_A_c
TDQS0_B_c-TDQS9_B_c
DQS0_A_t - DQS9_A_t
DQS0_B_t - DQS9_B_t
DQS0_A_c - DQS9_A_c
DQS0_B_c - DQS9_B_c
RSP_B_n
PWR_GOOD /FAIL_n
I/O Function: CK_t, CK_c
I/O Function: CA0_A - CA6_A, CA0_B - CA6_B, PAR_A, PAR_B
I/O Function: CS0_A_n - CS1_A_n, CS0_B_n - CS1_B_n
I/O Function: DQ0_A - DQ31_A, DQ0_B - DQ31_B
I/O Function: CB0_A - CB7_A, CB0_B - CB7_B
I/O Function: DQS0_A_t - DQS9_A_t, DQS0_A_c - DQS9_A_c, DQS0_B_t - DQS9_B_t, DQS0_B_c - DQS9_B_c
I/O Function: TDQS0_A_c-DQS9_A_c, TDQS0_B_c-DQS9_B_c
I/O Function: DM0_A_n-DM3_A_n, DM0_B_n-DM3_B_n
I/O Function: LBDQ
I/O Function: LBDQS
I/O Function: ALERT_n
I/O Function: RESET_n
I/O Function: SCL
I/O Function: SDA
I/O Function: SAA
I/O Function: RFU
I/O Function: PWR_GOOD
I/O Function: VIN_MGMT
I/O Function: VIN_BULK
I/O Function: VSS
Pin assignment - KEY position
Diagram title
Register input - clock enable / command/address
Register input - chip select
Register input - parity
Register input - clock true
Register input - clock complement
Register input - reset
Register input - loopback data
Register input - loopback strobe
Register input - alert
Register output A - command/address
Register output A - chip select 0
Register output A - clock
Register output A - reset
Register output A - error in
Register output A - loopback data
Register output A - loopback strobe
Register output B - command/address
Register output B - chip select 0
Register output B - clock
Register output B - reset
Register output B - error in
Register output B - loopback data
Register output B - loopback strobe
Central register block
DRAM placement (front row, page1 layout)
DRAM placement (back row, page1 layout)
Resistor note
A-side DRAM placement (page2)
A-side command/address bus
A-side data strobe / data bus mapping
B-side DRAM placement (page2)
B-side command/address bus
B-side data strobe / data bus mapping
ZQ resistor note
Supported Frequency Down Bin 3200C
Supported Frequency Down Bin 3200BN/3200B
Supported Frequency Down Bin 3200AN
Supported Frequency Down Bin 3600C
Supported Frequency Down Bin 3600BN/3600B
Supported Frequency Down Bin 3600AN
Supported Frequency Down Bin 4000C
Supported Frequency Down Bin 4000BN/4000B
Supported Frequency Down Bin 4000AN
Supported Frequency Down Bin 4400C
Supported Frequency Down Bin 4400BN/4400B
Supported Frequency Down Bin 4400AN
Supported Frequency Down Bin (default 4400B base) tCK(AVG)
Supported Frequency Down Bin 4800C
Supported Frequency Down Bin 4800BN
Supported Frequency Down Bin 4800B
Supported Frequency Down Bin 4800AN
Supported Frequency Down Bin (default base) tCK(AVG)
Default tolerance note
Module overall length (Front, outer)
Module length (Front, inner)
Front contact span (left group)
Front contact span (right group)
Front left edge dimension
Front edge dimension with tolerance
Registering Clock Driver callout
Front view detail callouts
Module height (Back view, right side)
Module height left dimension (Back)
Corner radius (Back)
Pin width / contact pitch (Side)
Detail A - contact dimension 0.85
Detail A - contact dimension 0.60±0.03
Detail of Contacts A, F label
Detail A - keep out note Max 0.30
Detail A - keep out note Max 0.35
Detail A - keep out note Max 0.25
Detail B - dimension 1.50±0.05
Detail B - dimension 0.2±0.15
Detail B - dimension 0.20±0.15
Detail B - dimension 5.95
Detail B - dimension 3.85±0.1
Detail B - dimension 4.30
Detail of Contacts B - Pin 39
Detail of Contacts B - Pin 51
Detail B - dimension 2.10
Detail B - dimension 2.60
Detail B - dimension 9.35
Detail B - dimension 10.20
Detail of Contacts C - Pin 122
Detail of Contacts C - Pin 110
Detail C - dimension 2.10 (top)
Detail C - dimension 2.60
Detail C - dimension 9.35
Detail C - dimension 10.20
Detail D - keep out note Max 0.30
Detail D - keep out note Max 0.35
Detail D - keep out note Max 0.30 (2)
Detail D - dimension 0.85
Detail D - dimension 0.60±0.03
Detail D - dimension 2.60
Detail D - dimension 3.35
Detail E - dimension 2.10±0.15
Detail E - dimension 2.70±0.15
Detail E - dimension 30.75
Detail E - dimension 17.60
Detail of Contacts E label
Pin reference - Pin 35
Pin reference - Pin 47
Pin reference - Pin 1
Pin reference - Pin 105
Pin reference - Pin 117
Detail F - dimension 8.00
Detail F - dimension 11.00
SPD component callout
TS component callout
Number of ranks
Number of Bank Groups
Block diagram title / module configuration
Central component (block diagram)
Register input - command/address
Register input - QLBD
Register input - QLBS
Register output A-side command/address
Register output A-side chip select
Register output A-side clock
Register output A-side reset
Register output A-side derror_in
Register output A-side DLBD
Register output A-side DLBS
Register output B-side command/address
Register output B-side chip select
Register output B-side clock
Register output B-side reset
Register output B-side derror_in
Register output B-side DLBD
Register output B-side DLBS
DRAM placement front row (block diagram)
DRAM placement back row (block diagram)
DRAM data byte routing - A side
DRAM placement A-side (page2 diagram)
Command/address bus A (page2 diagram)
DRAM data byte routing - B side
DRAM placement B-side (page2 diagram)
Command/address bus B (page2 diagram)
DRAM ZQ resistor note
Voltage on VDD pin relative to Vss (Absolute Maximum DC Rating)
Voltage on VDDQ pin relative to Vss (Absolute Maximum DC Rating)
Voltage on VPP pin relative to Vss (Absolute Maximum DC Rating)
Voltage on any pin relative to Vss (Absolute Maximum DC Rating)
Storage Temperature (Absolute Maximum DC Rating)
Device Supply Voltage VDD (Recommended DC Operating) Min.
Device Supply Voltage VDD (Recommended DC Operating) Typ.
Device Supply Voltage VDD (Recommended DC Operating) Max.
Device Supply Voltage VDD Z(f) Spec Freq: 2MHz to 10MHz Zmax
Device Supply Voltage VDD Z(f) Spec Freq: 20MHz Zmax
Supply Voltage for I/O VDDQ (Recommended DC Operating) Min.
Supply Voltage for I/O VDDQ (Recommended DC Operating) Typ.
Supply Voltage for I/O VDDQ (Recommended DC Operating) Max.
Supply Voltage for I/O VDDQ Z(f) Spec Freq: 2MHz to 10MHz Zmax
Supply Voltage for I/O VDDQ Z(f) Spec Freq: 20MHz Zmax
Core Power Voltage VPP (Recommended DC Operating) Min.
Core Power Voltage VPP (Recommended DC Operating) Typ.
Core Power Voltage VPP (Recommended DC Operating) Max.
Core Power Voltage VPP Z(f) Spec Freq: 2MHz to 10MHz Zmax
Core Power Voltage VPP Z(f) Spec Freq: 20MHz Zmax
Supported Frequency Down Bins - reference tAAmin
Supported Frequency Down Bins - reference Read CL/Write CWL
Supported Frequency Down Bins - reference tCK(AVG) min
Supported Frequency Down Bins - reference tCK(AVG) max
Down bin 3200C tAAmin
Down bin 3200C tRCDmin/tRPmin
Down bin 3200C Read CL/Write CWL
Down bin 3200C tCK(AVG) min
Down bin 3200C tCK(AVG) max
Down bin 3200BN / 3200B tAAmin
Down bin 3200BN / 3200B tRCDmin/tRPmin
Down bin 3200BN / 3200B Read CL/Write CWL
Down bin 3200BN / 3200B tCK(AVG) min
Down bin 3200BN / 3200B tCK(AVG) max
Down bin 3200AN tAAmin
Down bin 3200AN tRCDmin/tRPmin
Down bin 3200AN Read CL/Write CWL
Down bin 3200AN tCK(AVG)
Down bin 3600C tAAmin
Down bin 3600C tRCDmin/tRPmin
Down bin 3600C Read CL/Write CWL
Down bin 3600C tCK(AVG) min
Down bin 3600C tCK(AVG) max
Down bin 3600BN / 3600B tAAmin
Down bin 3600BN / 3600B tRCDmin/tRPmin
Down bin 3600BN / 3600B Read CL/Write CWL
Down bin 3600BN / 3600B tCK(AVG) min
Down bin 3600BN / 3600B tCK(AVG) max
Down bin 3600AN tAAmin
Down bin 3600AN tRCDmin/tRPmin
Down bin 3600AN Read CL/Write CWL
Down bin 3600AN tCK(AVG)
Down bin 4000C tAAmin
Down bin 4000C tRCDmin/tRPmin
Down bin 4000C Read CL/Write CWL
Down bin 4000C tCK(AVG) min
Down bin 4000C tCK(AVG) max
Down bin 4000BN / 4000B tAAmin
Down bin 4000BN / 4000B tRCDmin/tRPmin
Down bin 4000BN / 4000B Read CL/Write CWL
Down bin 4000BN / 4000B tCK(AVG) min
Down bin 4000BN / 4000B tCK(AVG) max
Down bin 4000AN tAAmin
Down bin 4000AN tRCDmin/tRPmin
Down bin 4000AN Read CL/Write CWL
Down bin 4000AN tCK(AVG)
Down bin 4400C tAAmin
Down bin 4400C tRCDmin/tRPmin
Down bin 4400C Read CL/Write CWL
Down bin 4400C tCK(AVG) min
Down bin 4400C tCK(AVG) max
Down bin 4400BN / 4400B tAAmin
Down bin 4400BN / 4400B tRCDmin/tRPmin
Down bin 4400BN / 4400B Read CL/Write CWL
Down bin 4400BN / 4400B tCK(AVG) min
Down bin 4400BN / 4400B tCK(AVG) max
Down bin 4400AN tAAmin
Down bin 4400AN tRCDmin/tRPmin
Down bin 4400AN Read CL/Write CWL
Down bin 4400AN tCK(AVG)
Down bin 4800C tAAmin
Down bin 4800C tRCDmin/tRPmin
Down bin 4800C Read CL/Write CWL
Down bin 4800C tCK(AVG) min
Down bin 4800C tCK(AVG) max
Down bin 4800BN tAAmin
Down bin 4800BN tRCDmin/tRPmin
Down bin 4800BN Read CL/Write CWL
Down bin 4800BN tCK(AVG) min
Down bin 4800BN tCK(AVG) max
Down bin 4800B tAAmin
Down bin 4800B tRCDmin/tRPmin
Down bin 4800B Read CL/Write CWL
Down bin 4800B tCK(AVG) min
Down bin 4800B tCK(AVG) max
Down bin 4800AN tAAmin
Down bin 4800AN tRCDmin/tRPmin
Down bin 4800AN Read CL/Write CWL
Down bin 4800AN tCK(AVG)
Module overall length (Front, outermost)
Module length (Front)
Module height (Front, left edge)
Module height (Front, inner)
Front feature offset
Front dimension (left contact group)
Front span (left contact group to key)
Front span (key to right contact group)
Front dimension (right contact group)
Registering Clock Driver tolerance
Back module height (right edge)
Detail of Contacts E - dimension
Detail of Contacts B - pin reference
Detail of Contacts C - pin reference
Detail of Contacts D - max dimension
Pin reference (front view)
Detail F component label
Detail B/D radius callouts
Bank configuration
Register input signals
Register A-side outputs
Register B-side outputs
DRAM placement front-side row (page1 lower diagram)
DRAM placement back-side row (page1 lower diagram)
Note 1 (resistor value)
DRAM placement A-channel (page2 upper diagram)
A-channel DQ/DQS routing (page2 upper diagram)
DRAM placement B-channel (page2 lower diagram)
B-channel DQ/DQS routing (page2 lower diagram)
Note 2 (ZQ resistor)
VDD - Voltage on VDD pin relative to Vss (Absolute Maximum DC Rating)
VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Maximum DC Rating)
VPP - Voltage on VPP pin relative to Vss (Absolute Maximum DC Rating)
VIN, VOUT - Voltage on any pin relative to Vss (Absolute Maximum DC Rating)
TSTG - Storage Temperature (Absolute Maximum DC Rating)
tREFI1 - REFab Normal, 0°C <= TCASE <= 85°C
tREFI1 - REFab Normal, 85°C < TCASE <= 95°C
tREFI2 - REFab Fine Granularity, 0°C <= TCASE <= 85°C
tREFI2 - REFab Fine Granularity, 85°C < TCASE <= 95°C
tREFIsb - REFsb Fine Granularity, 0°C <= TCASE <= 85°C
tREFIsb - REFsb Fine Granularity, 85°C < TCASE <= 95°C
VDD - Device Supply Voltage (Recommended DC Operating, Min.)
VDD - Device Supply Voltage (Recommended DC Operating, Typ.)
VDD - Device Supply Voltage (Recommended DC Operating, Max.)
VDD - Z(f) Spec Zmax, Freq: 2MHz to 10MHz (Recommended DC Operating)
VDD - Z(f) Spec Zmax, Freq: 20MHz (Recommended DC Operating)
VDDQ - Supply Voltage for I/O (Recommended DC Operating, Min.)
VDDQ - Supply Voltage for I/O (Recommended DC Operating, Typ.)
VDDQ - Supply Voltage for I/O (Recommended DC Operating, Max.)
VDDQ - Z(f) Spec Zmax, Freq: 2MHz to 10MHz (Recommended DC Operating)
VDDQ - Z(f) Spec Zmax, Freq: 20MHz (Recommended DC Operating)
VPP - Core Power Voltage (Recommended DC Operating, Min.)
VPP - Core Power Voltage (Recommended DC Operating, Typ.)
VPP - Core Power Voltage (Recommended DC Operating, Max.)
VPP - Z(f) Spec Zmax, Freq: 2MHz to 10MHz (Recommended DC Operating)
VPP - Z(f) Spec Zmax, Freq: 20MHz (Recommended DC Operating)
Internal read command to first data
ACT to internal read or write delay time
Row Precharge Time
ACT to PRE command period
ACT to ACT or REF command period
CAS Write Latency
tAAmin
tCK(AVG) min
tCK(AVG) max
Read CL / Write CWL
tRCDmin/tRPmin
tCK(AVG)
Dimension units
Module overall width (Front, top)
Notch/feature offset (Front, left)
Contact span dimension (Front)
Contact group dimension (Front, left segment)
Contact group dimension (Front, right segment)
Module height (Back view)
Feature height dimension (Back view)
Edge radius (Back)
Module thickness / feature dimension (Side, max)
Detail of Contacts A, F - contact length
Detail of Contacts A, F - contact dimension
Detail of Contacts D - contact length
Detail of Contacts D - contact dimension
Non-metalized keep out area (Detail B/D)
Keep out area - max dimension
Non-metalized keep out area (Detail D)
Keep out area - max dimension (Detail D)
Module length dimension (overall)
Module length dimension
Pin callout
Module height dimension (Back, side)
General tolerance value
Pin callout (Front detail)
Bank groups
Generation
Absolute Maximum: Voltage on VDD pin relative to Vss (VDD)
Absolute Maximum: Voltage on VDDQ pin relative to Vss (VDDQ)
Absolute Maximum: Voltage on VPP pin relative to Vss (VPP)
Absolute Maximum: Voltage on any pin relative to Vss (VIN, VOUT)
Absolute Maximum: Storage Temperature (TSTG)
tREFI1 REFab Normal, 0°C <= TCASE <= 85°C (expression rREFI)
tREFI1 REFab Normal, 85°C < TCASE <= 95°C (expression rREFI/2)
tREFI2 REFab Fine Granularity, 0°C <= TCASE <= 85°C (expression rREFI/2)
tREFI2 REFab Fine Granularity, 85°C < TCASE <= 95°C (expression rREFI/4)
tREFIsb REFsb Fine Granularity, 0°C <= TCASE <= 85°C (expression rREFI/(2*n))
tREFIsb REFsb Fine Granularity, 85°C < TCASE <= 95°C (expression rREFI/(4*n))
Recommended DC: Device Supply Voltage (VDD) Min
Recommended DC: Device Supply Voltage (VDD) Typ
Recommended DC: Device Supply Voltage (VDD) Max
Recommended DC: VDD Z(f) Spec DC to 2MHz Zmax
Recommended DC: VDD Z(f) Spec 20MHz Zmax
Recommended DC: Supply Voltage for I/O (VDDQ) Min
Recommended DC: Supply Voltage for I/O (VDDQ) Typ
Recommended DC: Supply Voltage for I/O (VDDQ) Max
Recommended DC: VDDQ Z(f) Spec DC to 2MHz Zmax
Recommended DC: VDDQ Z(f) Spec 20MHz Zmax
Recommended DC: Core Power Voltage (VPP) Min
Recommended DC: Core Power Voltage (VPP) Typ
Recommended DC: Core Power Voltage (VPP) Max
Recommended DC: VPP Z(f) Spec DC to 2MHz Zmax
Recommended DC: VPP Z(f) Spec 20MHz Zmax
CA Rx Mask voltage p-p (VciVW) Max
CA Rx Timing Window (TcIVW) Max
CA Input Slew Rate over VcIVW (SRIN_cIVW) Min
CA Input Slew Rate over VcIVW (SRIN_cIVW) Max
Rj RMS value of N-UI Jitter, N=4..30 (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter, N=4..30 (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter, N=4..30 (tCK_NUI_Tj_NoBUJ) Max
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max
Differential input high measurement level CK_t,CK_c (VIHdiffCK)
Differential input low measurement level CK_t,CK_c (VILdiffCK)
Degradation of timing width with DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) Max
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max
Differential input high measurement level DQS_t,DQS_c (VIHdiffDQS)
Differential input low measurement level DQS_t,DQS_c (VILdiffDQS)
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected Random wide band (10 MHz-1 GHz) Jitter (Rj_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected Random wide band (10 MHz-1 GHz) Jitter (Rj_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected voltage noise as PRBS23 / at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected voltage noise as PRBS23 / at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max
Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics)
Connectivity Test Mode timing tCT_IS Min
Connectivity Test Mode timing tCT_Enable Min
Connectivity Test Mode timing tCT_Valid Max
RON34Pd VOLdc=0.5*VDDQ Unit
RON34Pd VOMdc=0.8*VDDQ Nom
RON34Pd VOMdc=0.8*VDDQ Unit
RON34Pd VOHdc=0.95*VDDQ Nom
RON34Pd VOHdc=0.95*VDDQ Unit
RON34Pu VOLdc=0.5*VDDQ Nom
RON34Pu VOLdc=0.5*VDDQ Unit
RON34Pu VOMdc=0.8*VDDQ Nom
RON34Pu VOMdc=0.8*VDDQ Unit
RON34Pu VOHdc=0.95*VDDQ Nom
RON34Pu VOHdc=0.95*VDDQ Unit
RON48Pd VOLdc=0.5*VDDQ Nom
RON48Pd VOLdc=0.5*VDDQ Unit
RON48Pd VOMdc=0.8*VDDQ Nom
RON48Pd VOMdc=0.8*VDDQ Unit
RON48Pd VOHdc=0.95*VDDQ Nom
RON48Pd VOHdc=0.95*VDDQ Unit
RON48Pu VOLdc=0.5*VDDQ Nom
RON48Pu VOLdc=0.5*VDDQ Unit
RON48Pu VOMdc=0.8*VDDQ Nom
RON48Pu VOMdc=0.8*VDDQ Unit
RON48Pu VOHdc=0.95*VDDQ Nom
RON48Pu VOHdc=0.95*VDDQ Unit
LB RON34Pd VOLdc=0.5*VDDQ Nom
LB RON34Pd VOLdc=0.5*VDDQ Unit
LB RON34Pd VOMdc=0.8*VDDQ Nom
LB RON34Pd VOMdc=0.8*VDDQ Unit
LB RON34Pd VOHdc=0.95*VDDQ Nom
LB RON34Pd VOHdc=0.95*VDDQ Unit
LB RON34Pu VOLdc=0.5*VDDQ Nom
LB RON34Pu VOLdc=0.5*VDDQ Unit
LB RON34Pu VOMdc=0.8*VDDQ Nom
LB RON34Pu VOMdc=0.8*VDDQ Unit
LB RON34Pu VOHdc=0.95*VDDQ Nom
LB RON34Pu VOHdc=0.95*VDDQ Unit
Loopback LBDQS Output Low Time (tLBQSL) DDR5-3200 MIN
Loopback LBDQS Output Low Time (tLBQSL) DDR5-3200 MAX
Loopback LBDQS Output Low Time (tLBQSL) DDR5-3600 MIN
Loopback LBDQS Output Low Time (tLBQSL) DDR5-3600 MAX
Loopback LBDQS Output Low Time (tLBQSL) DDR5-4000 MIN
Loopback LBDQS Output Low Time (tLBQSL) DDR5-4000 MAX
Loopback LBDQS Output Low Time (tLBQSL) DDR5-4400 MIN
Loopback LBDQS Output Low Time (tLBQSL) DDR5-4400 MAX
Loopback LBDQS Output Low Time (tLBQSL) DDR5-4800 MIN
Loopback LBDQS Output Low Time (tLBQSL) DDR5-4800 MAX
Loopback LBDQS Output High Time (tLBQSH) DDR5-3200 MIN
Loopback LBDQS Output High Time (tLBQSH) DDR5-3200 MAX
Loopback LBDQS Output High Time (tLBQSH) DDR5-3600 MIN
Loopback LBDQS Output High Time (tLBQSH) DDR5-3600 MAX
Loopback LBDQS Output High Time (tLBQSH) DDR5-4000 MIN
Loopback LBDQS Output High Time (tLBQSH) DDR5-4000 MAX
Loopback LBDQS Output High Time (tLBQSH) DDR5-4400 MIN
Loopback LBDQS Output High Time (tLBQSH) DDR5-4400 MAX
Loopback LBDQS Output High Time (tLBQSH) DDR5-4800 MIN
Loopback LBDQS Output High Time (tLBQSH) DDR5-4800 MAX
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3200 MIN
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3200 MAX
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3600 MIN
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-3600 MAX
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4000 MIN
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4000 MAX
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4400 MIN
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4400 MAX
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4800 MIN
Loopback LBDQS to LBDQ Skew (tLBDQSQ) DDR5-4800 MAX
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3200 MIN
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3200 MAX
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3600 MIN
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-3600 MAX
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4000 MIN
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4000 MAX
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4400 MIN
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4400 MAX
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4800 MIN
Loopback LBDQ Output Time from LBDQS (tLBQH) DDR5-4800 MAX
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3200 MIN
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3200 MAX
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3600 MIN
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-3600 MAX
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4000 MIN
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4000 MAX
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4400 MIN
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4400 MAX
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4800 MIN
Loopback Data valid window (tLBQH-tLBDQSQ) (tLBDVW) DDR5-4800 MAX
Alert_n RONPd VOLdc=0.1*VDDQ Unit
Alert_n RONPd VOMdc=0.8*VDDQ Unit
Alert_n RONPd VOHdc=0.95*VDDQ Unit
CT RONPd_CT VOBdc=0.2xVDDQ Max
CT RONPd_CT VOLdc=0.5xVDDQ Max
CT RONPd_CT VOMdc=0.8xVDDQ Max
CT RONPd_CT VOHdc=0.95xVDDQ Max
CT RONPu_CT VOBdc=0.2xVDDQ Max
CT RONPu_CT VOLdc=0.5xVDDQ Max
CT RONPu_CT VOMdc=0.8xVDDQ Max
CT RONPu_CT VOHdc=0.95xVDDQ Max
CT uncalibrated drive strength tolerance
Single ended output slew rate SRQse DDR5-3200 MIN
Single ended output slew rate SRQse DDR5-3200 MAX
Single ended output slew rate SRQse DDR5-3600 MIN
Single ended output slew rate SRQse DDR5-3600 MAX
Single ended output slew rate SRQse DDR5-4000 MIN
Single ended output slew rate SRQse DDR5-4000 MAX
Single ended output slew rate SRQse DDR5-4400 MIN
Single ended output slew rate SRQse DDR5-4400 MAX
Single ended output slew rate SRQse DDR5-4800 MIN
Single ended output slew rate SRQse DDR5-4800 MAX
Differential output slew rate SRQdiff DDR5-3200 MIN
Differential output slew rate SRQdiff DDR5-3200 MAX
Differential output slew rate SRQdiff DDR5-3600 MIN
Differential output slew rate SRQdiff DDR5-3600 MAX
Differential output slew rate SRQdiff DDR5-4000 MIN
Differential output slew rate SRQdiff DDR5-4000 MAX
Differential output slew rate SRQdiff DDR5-4400 MIN
Differential output slew rate SRQdiff DDR5-4400 MAX
Differential output slew rate SRQdiff DDR5-4800 MIN
Differential output slew rate SRQdiff DDR5-4800 MAX
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3200 MIN
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3200 MAX
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3200 MIN
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3200 MAX
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3200 MIN
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3200 MAX
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3200 MIN
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3200 MAX
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3600 MIN
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-3600 MAX
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3600 MIN
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-3600 MAX
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3600 MIN
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-3600 MAX
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3600 MIN
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-3600 MAX
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4000 MIN
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4000 MAX
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4000 MIN
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4000 MAX
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4000 MIN
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4000 MAX
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4000 MIN
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4000 MAX
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4400 MIN
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4400 MAX
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4400 MIN
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4400 MAX
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4400 MIN
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4400 MAX
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4400 MIN
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4400 MAX
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4800 MIN
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) DDR5-4800 MAX
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4800 MIN
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) DDR5-4800 MAX
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4800 MIN
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) DDR5-4800 MAX
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4800 MIN
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) DDR5-4800 MAX
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3200 MIN
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3200 MAX
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3200 MIN
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3200 MAX
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3200 MIN
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3200 MAX
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3200 MIN
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3200 MAX
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3200 MIN
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3200 MAX
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3600 MIN
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-3600 MAX
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3600 MIN
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-3600 MAX
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3600 MIN
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-3600 MAX
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3600 MIN
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-3600 MAX
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3600 MIN
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-3600 MAX
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4000 MIN
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4000 MAX
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4000 MIN
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4000 MAX
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4000 MIN
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4000 MAX
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4000 MIN
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4000 MAX
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4000 MIN
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4000 MAX
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4400 MIN
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4400 MAX
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4400 MIN
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4400 MAX
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4400 MIN
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4400 MAX
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4400 MIN
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4400 MAX
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4400 MIN
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4400 MAX
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4800 MIN
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) DDR5-4800 MAX
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4800 MIN
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) DDR5-4800 MAX
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4800 MIN
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) DDR5-4800 MAX
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4800 MIN
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) DDR5-4800 MAX
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4800 MIN
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) DDR5-4800 MAX
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3200 MIN
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3200 MAX
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3600 MIN
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-3600 MAX
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4000 MIN
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4000 MAX
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4400 MIN
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4400 MAX
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4800 MIN
Eye Height skew DQ/DQS 1UI (TxEH_DQ_SES_1UI) DDR5-4800 MAX
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3200 MIN
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3200 MAX
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3600 MIN
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-3600 MAX
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4000 MIN
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4000 MAX
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4400 MIN
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4400 MAX
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4800 MIN
Eye Width skew DQ/DQS 1UI (TxEW_DQ_SES_1UI) DDR5-4800 MAX
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3200 MIN
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3200 MAX
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3600 MIN
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-3600 MAX
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4000 MIN
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4000 MAX
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4400 MIN
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4400 MAX
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4800 MIN
Eye Height skew DQ/DQS 2UI (TxEH_DQ_SES_2UI) DDR5-4800 MAX
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3200 MIN
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3200 MAX
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3600 MIN
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-3600 MAX
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4000 MIN
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4000 MAX
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4400 MIN
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4400 MAX
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4800 MIN
Eye Width skew DQ/DQS 2UI (TxEW_DQ_SES_2UI) DDR5-4800 MAX
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3200 MIN
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3200 MAX
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3600 MIN
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-3600 MAX
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4000 MIN
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4000 MAX
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4400 MIN
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4400 MAX
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4800 MIN
Eye Height skew DQ/DQS 3UI (TxEH_DQ_SES_3UI) DDR5-4800 MAX
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3200 MIN
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3200 MAX
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3600 MIN
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-3600 MAX
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4000 MIN
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4000 MAX
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4400 MIN
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4400 MAX
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4800 MIN
Eye Width skew DQ/DQS 3UI (TxEW_DQ_SES_3UI) DDR5-4800 MAX
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3200 MIN
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3200 MAX
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3600 MIN
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-3600 MAX
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4000 MIN
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4000 MAX
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4400 MIN
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4400 MAX
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4800 MIN
Eye Height skew DQ/DQS 4UI (TxEH_DQ_SES_4UI) DDR5-4800 MAX
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3200 MIN
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3200 MAX
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3600 MIN
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-3600 MAX
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4000 MIN
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4000 MAX
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4400 MIN
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4400 MAX
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4800 MIN
Eye Width skew DQ/DQS 4UI (TxEW_DQ_SES_4UI) DDR5-4800 MAX
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3200 MIN
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3200 MAX
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3600 MIN
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-3600 MAX
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4000 MIN
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4000 MAX
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4400 MIN
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4400 MAX
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4800 MIN
Eye Height skew DQ/DQS 5UI (TxEH_DQ_SES_5UI) DDR5-4800 MAX
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3200 MIN
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3200 MAX
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3600 MIN
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-3600 MAX
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4000 MIN
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4000 MAX
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4400 MIN
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4400 MAX
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4800 MIN
Eye Width skew DQ/DQS 5UI (TxEW_DQ_SES_5UI) DDR5-4800 MAX
Default tolerance on all dimensions unless otherwise stated
Module dimension (Front, second)
Front dimension (left segment)
Front dimension (right segment)
Front dimension (left vertical)
Front dimension (right vertical)
Front dimension (3.00)
Front feature dimension
Contact pitch (Registering Clock Driver area)
Module height (Back, vertical)
Back dimension (17.60)
Back dimension (31.25)
Detail of Contacts A,F - dimension 0.85
Detail of Contacts A,F - dimension 0.60
Detail of Contacts A,F - dimension 1.50
Detail of Contacts A,F - dimension 0.2
Detail of Contacts A,F - dimension 0.20
Detail of Contacts A,F - dimension 5.95
Detail of Contacts A,F - dimension 3.85
Detail of Contacts A,F - dimension 4.30
Detail of Contacts A,F - Pin 35
Detail of Contacts A,F - Pin 47
Detail of Contacts A,F - Pin 1
Detail of Contacts A,F - Pin 105
Detail of Contacts A,F - Pin 117
Detail of Contacts B - dimension 2.10
Detail of Contacts B - dimension 2.60
Detail of Contacts B - dimension 9.35
Detail of Contacts B - dimension 10.20
Detail of Contacts C - dimension 2.10
Detail of Contacts C - dimension 2.60
Detail of Contacts C - dimension 9.35
Detail of Contacts C - dimension 10.20
Detail of Contacts D - dimension 2.10
Detail of Contacts D - dimension 0.85
Detail of Contacts D - dimension 0.60
Detail of Contacts D - dimension 2.60
Detail of Contacts D - Non-matarized keep out area Max 0.30
Detail of Contacts D - Max 0.35
Detail of Contacts D - Max 0.30 (second)
Detail of Contacts D - dimension 3.35
Detail of Contacts E - Non-matarized keep out area Max 0.30
Detail of Contacts E - Max 0.35
Detail of Contacts E - Max 0.25
Detail E - dimension 2.10
Detail E - dimension 8.00
Detail E - dimension 11.00
Component label - Registering Clock Driver
Component label - SPD
Component label - TS
REFab Normal tREFI1 (0°C <= TCASE <= 85°C)
REFab Normal tREFI1 (85°C < TCASE <= 95°C)
REFab Fine Granularity tREFI2 (0°C <= TCASE <= 85°C)
REFab Fine Granularity tREFI2 (85°C < TCASE <= 95°C)
REFsb Fine Granularity tREFIsb (0°C <= TCASE <= 85°C)
REFsb Fine Granularity tREFIsb (85°C < TCASE <= 95°C)
VDD Device Supply Voltage Min
VDD Device Supply Voltage Typ
VDD Device Supply Voltage Max
VDD Z(f) Spec 2MHz-10MHz Zmax
VDDQ Supply Voltage for I/O Min
VDDQ Supply Voltage for I/O Typ
VDDQ Supply Voltage for I/O Max
VDDQ Z(f) Spec 2MHz-10MHz Zmax
VPP Core Power Voltage Min
VPP Core Power Voltage Typ
VPP Core Power Voltage Max
VPP Z(f) Spec 2MHz-10MHz Zmax
Rj RMS value of N-UI Jitter (N=2,3) (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter (N=2,3) (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter (N=2,3) (tCK_NUI_Tj_NoBUJ) Max
Rj RMS value of N-UI Jitter (N=4..30) (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter (N=4..30) (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter (N=4..30) (tCK_NUI_Tj_NoBUJ) Max
DRAM Reference clock frequency tCK Min
DRAM Reference clock frequency tCK Max
Clock differential input crosspoint voltage ratio VIX_CK_Ratio Max (DDR5-3200-4800)
Clock differential input crosspoint voltage ratio VIX_CK_Ratio Max (DDR5-6800-8400)
Input Clock Voltage Sensitivity (differential pp) VRx_CK Max
VIHdiffCK Differential input high measurement level (CK_t, CK_c) (DDR5 3200-6400)
VILdiffCK Differential input low measurement level (CK_t, CK_c) (DDR5 3200-6400)
Delay of any data lane relative to the DQS_t/DQS_c crossing (tRx_DQS2DQ) Min
Delay of any data lane relative to the DQS_t/DQS_c crossing (tRx_DQS2DQ) Max
Applied DCD and Rj RMS to the DQS Max
DQS Rx Input Voltage Sensitivity (differential pp) VRx_DQS Max
DQS differential input crosspoint voltage ratio VIX_DQS_Ratio Max (DDR5-3200-4800)
VIHdiffDQS Differential input high measurement level (DQS_t, DQS_c) (DDR5 3200-6400)
VILdiffDQS Differential input low measurement level (DQS_t, DQS_c) (DDR5 3200-6400)
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) Max
Minimum DQ Rx input voltage sensitivity applied around Vref VRx_DQ Max
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected voltage noise as PRBS23, or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected voltage noise as PRBS23, or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max
Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics) Min
Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics) Max
tCT_IS Min
tCT_Enable Min
tCT_Valid Max
TEN AC Input High Voltage VIH(AC)_TEN Min
TEN AC Input High Voltage VIH(AC)_TEN Max
TEN DC Input High Voltage VIH(DC)_TEN Min
TEN DC Input High Voltage VIH(DC)_TEN Max
TEN DC Input Low Voltage VIL(DC)_TEN Min
TEN DC Input Low Voltage VIL(DC)_TEN Max
TEN AC Input Low Voltage VIL(AC)_TEN Min
TEN AC Input Low Voltage VIL(AC)_TEN Max
TEN Input signal Falling time TF_input_TEN Max
TEN Input signal Rising time TR_input_TEN Max
VIH(AC)_RESET AC Input High Voltage Min
VIH(AC)_RESET AC Input High Voltage Max
VIH(DC)_RESET DC Input High Voltage Min
VIH(DC)_RESET DC Input High Voltage Max
VIL(DC)_RESET DC Input Low Voltage Min
VIL(DC)_RESET DC Input Low Voltage Max
VIL(AC)_RESET AC Input Low Voltage Min
VIL(AC)_RESET AC Input Low Voltage Max
TR_RESET Rising time Max
tPW_RESET RESET pulse width Min
34Ω RON34Pd VOLdc= 0.5*VDDQ Min
34Ω RON34Pd VOLdc= 0.5*VDDQ Nom
34Ω RON34Pd VOLdc= 0.5*VDDQ Max
34Ω RON34Pd VOMdc= 0.8*VDDQ Min
34Ω RON34Pd VOMdc= 0.8*VDDQ Nom
34Ω RON34Pd VOMdc= 0.8*VDDQ Max
34Ω RON34Pd VOHdc= 0.95*VDDQ Min
34Ω RON34Pd VOHdc= 0.95*VDDQ Nom
34Ω RON34Pd VOHdc= 0.95*VDDQ Max
34Ω RON34Pu VOLdc= 0.5*VDDQ Min
34Ω RON34Pu VOLdc= 0.5*VDDQ Nom
34Ω RON34Pu VOLdc= 0.5*VDDQ Max
34Ω RON34Pu VOMdc= 0.8*VDDQ Min
34Ω RON34Pu VOMdc= 0.8*VDDQ Nom
34Ω RON34Pu VOMdc= 0.8*VDDQ Max
34Ω RON34Pu VOHdc= 0.95*VDDQ Min
34Ω RON34Pu VOHdc= 0.95*VDDQ Nom
34Ω RON34Pu VOHdc= 0.95*VDDQ Max
48Ω RON48Pd VOLdc= 0.5*VDDQ Min
48Ω RON48Pd VOLdc= 0.5*VDDQ Nom
48Ω RON48Pd VOLdc= 0.5*VDDQ Max
48Ω RON48Pd VOMdc= 0.8*VDDQ Min
48Ω RON48Pd VOMdc= 0.8*VDDQ Nom
48Ω RON48Pd VOMdc= 0.8*VDDQ Max
48Ω RON48Pd VOHdc= 0.95*VDDQ Min
48Ω RON48Pd VOHdc= 0.95*VDDQ Nom
48Ω RON48Pd VOHdc= 0.95*VDDQ Max
48Ω RON48Pu VOLdc= 0.5*VDDQ Min
48Ω RON48Pu VOLdc= 0.5*VDDQ Nom
48Ω RON48Pu VOLdc= 0.5*VDDQ Max
48Ω RON48Pu VOMdc= 0.8*VDDQ Min
48Ω RON48Pu VOMdc= 0.8*VDDQ Nom
48Ω RON48Pu VOMdc= 0.8*VDDQ Max
48Ω RON48Pu VOHdc= 0.95*VDDQ Min
48Ω RON48Pu VOHdc= 0.95*VDDQ Nom
48Ω RON48Pu VOHdc= 0.95*VDDQ Max
Mismatch between pull-up and pull-down MMPuPd (VOMdc=0.8*VDDQ) Min
Mismatch between pull-up and pull-down MMPuPd (VOMdc=0.8*VDDQ) Max
Mismatch DQ-DQ within byte variation pull-up MMPudd (VOMdc=0.8*VDDQ) Max
Mismatch DQ-DQ within byte variation pull-dn MMPddd (VOMdc=0.8*VDDQ) Max
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Min
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Nom
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Max
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Min
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Nom
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Max
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Min
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Nom
Loopback 34Ω RON34Pd (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Max
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Min
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Nom
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOLdc= 0.5*VDDQ Max
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Min
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Nom
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOMdc= 0.8*VDDQ Max
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Min
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Nom
Loopback 34Ω RON34Pu (LBDQS/LBDQ) VOHdc= 0.95*VDDQ Max
Loopback Mismatch between pull-up and pull-down MMPuPd Min
Loopback Mismatch between pull-up and pull-down MMPuPd Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd Max
Loopback LBDQS Output Low Time tLBQSL Min
Loopback LBDQS Output High Time tLBQSH Min
Loopback LBDQS to LBDQ Skew tLBDQSQ Min
Loopback LBDQ Output Time from LBDQS tLBQH Min
Loopback Data valid window (tLBQH-tLBDQSQ) tLBDVW Min
CT Mode 34Ω RONPd_CT VOBdc = 0.2 x VDDQ Max
CT Mode 34Ω RONPd_CT VOLdc = 0.5 x VDDQ Max
CT Mode 34Ω RONPd_CT VOMdc = 0.8 x VDDQ Max
CT Mode 34Ω RONPd_CT VOHdc = 0.95 x VDDQ Max
CT Mode 34Ω RONPu_CT VOBdc = 0.2 x VDDQ Max
CT Mode 34Ω RONPu_CT VOLdc = 0.5 x VDDQ Max
CT Mode 34Ω RONPu_CT VOMdc = 0.8 x VDDQ Max
CT Mode 34Ω RONPu_CT VOHdc = 0.95 x VDDQ Max
CT Mode uncalibrated drive strength tolerance
VOH Output high measurement level (for output SR) (DDR5-3200-6400)
VOL Output low measurement level (for output SR) (DDR5-3200-6400)
VOH Output high measurement level for Loopback Signals (DDR5-3200-6400)
VOL Output low measurement level for Loopback Signals (DDR5-3200-6400)
Single ended output slew rate SRQse Min
Single ended output slew rate SRQse Max
VOHdiff Differential output high measurement level (for output SR) (DDR5-3200-6400)
VOLdiff Differential output low measurement level (for output SR) (DDR5-3200-6400)
Differential output slew rate SRQdiff Min
Differential output slew rate SRQdiff Max
Rj RMS Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Rj_NoBUJ Max
Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ Max
Rj RMS Value of N-UI jitter without BUJ (1<N<4) tTx_DQS_NUI_Rj_NoBUJ Max
Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ Max
Rj RMS of 1-UI jitter without BUJ tTx_DQ_1UI_Rj_NoBUJ Max
Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ Max
Rj RMS of N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Rj_NoBUJ Max
Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ Max
Delay of any data lane relative to strobe lane tTx_DQS2DQ Min
Delay of any data lane relative to strobe lane tTx_DQS2DQ Max
Eye Height at transmitter with DQ-DQS skew of 1UI TxEH_DQ_SES_1UI Min
Eye Width at transmitter with DQ-DQS skew of 1UI TxEW_DQ_SES_1UI Min
Eye Height at transmitter with DQ-DQS skew of 2UI TxEH_DQ_SES_2UI Min
Eye Width at transmitter with DQ-DQS skew of 2UI TxEW_DQ_SES_2UI Min
Eye Height at transmitter with DQ-DQS skew of 3UI TxEH_DQ_SES_3UI Min
Eye Width at transmitter with DQ-DQS skew of 3UI TxEW_DQ_SES_3UI Min
Eye Height at transmitter with DQ-DQS skew of 4UI TxEH_DQ_SES_4UI Min
Eye Width at transmitter with DQ-DQS skew of 4UI TxEW_DQ_SES_4UI Min
Eye Height at transmitter with DQ-DQS skew of 5UI TxEH_DQ_SES_5UI Min
Eye Width at transmitter with DQ-DQS skew of 5UI TxEW_DQ_SES_5UI Min
IDD measurement: '0'/'LOW' defined
IDD measurement: '1'/'HIGH' defined
IDD measurement: 'MID-LEVEL' defined
IDD measurement: TCASE range
IDDQ0F current definition
IPP0F current definition
IDDQ2N current definition
IPP2N current definition
IDDQ2NT (Optional) current definition
IPP2NT (Optional) current definition
IDDQ2P current definition
IPP2P current definition
IDDQ3N current definition
IPP3N current definition
IDDQ3P current definition
IPP3P current definition
IDDQ4R current definition
IPP4R current definition
IDDQ4W current definition
IPP4W current definition
IDDQ5B current definition
IPP5B current definition
IDDQ5F current definition
IPP5F current definition
IDDQ5C current definition
IPP5C current definition
IDDQ6N current definition
IPP6N current definition
IDDQ6E current definition
IPP6E current definition
IDDQ7 current definition
IPP7 current definition
IDDQ8 current definition
IPP8 current definition
IDDQ9 (Optional) current definition
IPP9 (Optional) current definition
IDD6N TCASE Normal Temperature Range
IDD6E TCASE Extended Temperature Range
IDD measurement Burst Length
IDD measurement Pull-Up Output Driver Impedance Control
IDD measurement Pull-Down Output Driver Impedance Control
IDD measurement RTT_NOM_WR = RTT_NOM_RD
IDD measurement RTT_WR
DDR5-4400 Speed Bin
CL-nRCD-nRP (DDR5-4400B)
Down Bin 3200C tAAmin
Down Bin 3200C tRCDmin/tRPmin
Down Bin 3200C Read CL / Write CWL
Down Bin 3200C tCK(AVG) min
Down Bin 3200C tCK(AVG) max
Down Bin labels (3200)
Down Bin 3200B/3200BN tAAmin
Down Bin 3200B Read CL / Write CWL
Down Bin 3200AN tAAmin
Down Bin 3200AN Read CL / Write CWL
Down Bin 3200AN tCK(AVG)
Down Bin 3600C tAAmin
Down Bin 3600C Read CL / Write CWL
Down Bin 3600C tCK(AVG) min
Down Bin 3600C tCK(AVG) max
Down Bin 3600B/3600BN tAAmin
Down Bin 3600B Read CL / Write CWL
Down Bin 3600AN tAAmin
Down Bin 3600AN Read CL / Write CWL
Down Bin 4000C tAAmin
Down Bin 4000C tRCDmin/tRPmin
Down Bin 4000C Read CL / Write CWL
Down Bin 4000C tCK(AVG) min
Down Bin 4000C tCK(AVG) max
Down Bin 4000B/4000BN tAAmin
Down Bin 4000B Read CL / Write CWL
Down Bin 4000AN tAAmin
Down Bin 4000AN Read CL / Write CWL
Down Bin 4400C tAAmin
Down Bin 4400C tRCDmin/tRPmin
Down Bin 4400C Read CL / Write CWL
Down Bin 4400C tCK(AVG) min
Down Bin 4400C tCK(AVG) max
Down Bin 4400B/4400BN tAAmin
Down Bin 4400B Read CL / Write CWL
Down Bin 4400AN tAAmin
Down Bin 4400AN Read CL / Write CWL
Top down bin tCK(AVG) (default)
DDR5-4800 Speed Bin
CL-nRCD-nRP (DDR5-4800B)
Internal read command to first data (tAA) [4800B]
ACT to internal read or write delay time (tRCD) [4800B]
Row Precharge Time (tRP) [4800B]
ACT to PRE command period (tRAS) [4800B]
ACT to ACT or REF command period (tRC) [4800B]
CAS Write Latency (CWL) [4800B]
Down Bin 4800C tAAmin
Down Bin 4800C Read CL / Write CWL
Down Bin 4800C tCK(AVG) min
Down Bin 4800C tCK(AVG) max
Down Bin 4800BN tAAmin
Down Bin 4800BN Read CL / Write CWL
Down Bin 4800B tAAmin
Down Bin 4800B tRCDmin/tRPmin
Down Bin 4800B Read CL / Write CWL
Down Bin 4800AN tAAmin
Down Bin 4800AN Read CL / Write CWL
Front dimension (Detail A region)
Front dimension left segment
Front dimension right segment
Front label
Detail A label
Detail B label
Detail C label
Detail D label
Detail E label
Detail F label
Back overall height
Back dimension (left)
Back dimension (left, secondary)
Back label
Back chamfer / corner radius
Side max thickness callout
Side label
Detail A,F width
Detail B dimension (contact)
Detail of Contacts B label
Detail C dimension (contact)
Detail of Contacts C label
Detail D non-metalized keepout note
Detail of Contacts D label
Address Table mapping
Block diagram - module configuration
Register device
Register input control signals (Channel A)
Register output signals (A-side)
Register output signals (B-side)
Control-bus DRAM daisy chain (front row)
Control-bus DRAM daisy chain (back row)
Default resistor value (block diagram note)
Default resistor tolerance (block diagram note)
Data-bus DRAM placement (A-side, front)
Data-bus signal assignment (A-side)
Data-bus DRAM placement (B-side, front)
Data-bus signal assignment (B-side)
Data-bus resistor value (note)
DRAM ZQ pin resistor (note)
VIN, VOUT
TSTG
tREFI1 (REFab Normal)
tREFI2 (REFab Fine Granularity)
tREFIsb (REFsb Fine Granularity)
VDD Device Supply Voltage
VDD Z(f) Spec 2MHz to 10MHz
VDD Z(f) Spec 20MHz
VDDQ Supply Voltage for I/O
VDDQ Z(f) Spec 2MHz to 10MHz
VDDQ Z(f) Spec 20MHz
VPP Core Power Voltage
VPP Z(f) Spec 2MHz to 10MHz
VPP Z(f) Spec 20MHz
Rx Mask voltage - p-p (VciVW)
Rx Timing Window (TcIVW)
Input Slew Rate over VcIVW (SRIN_cIVW)
Duty Cycle Error (tCK_Duty_UI_Error)
Differential input high measurement level (VIHdiffDQS)
Differential input low measurement level (VILdiffDQS)
Differential Input slew rate for rising edge (DQS_t, DQS_c) - Defined by
Differential Input slew rate for falling edge (DQS_t, DQS_c) - Defined by
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) Min
Connectivity Test (CT) Mode AC parameter tCT_IS Min
Connectivity Test (CT) Mode AC parameter tCT_Enable Min
Connectivity Test (CT) Mode AC parameter tCT_Valid Max
Output Driver Table 20 condition
Loopback Output Driver Table 21 condition
LB Mismatch pull-up/pull-down MMPuPd Min
LB Mismatch pull-up/pull-down MMPuPd Max
Loopback LBDQS Output Low Time MIN
Loopback LBDQS Output Low Time MAX
Loopback LBDQS Output High Time MIN
Loopback LBDQS Output High Time MAX
Loopback LBDQS to LBDQ Skew MIN
Loopback LBDQS to LBDQ Skew MAX
Loopback LBDQ Output Time from LBDQS MIN
Loopback LBDQ Output Time from LBDQS MAX
Loopback Data valid window per UI per DRAM MIN
Loopback Data valid window per UI per DRAM MAX
Table 22 note
Alert RONPd Min @ VOLdc=0.1*VDDQ
Alert RONPd Max @ VOLdc=0.1*VDDQ
Alert RONPd Min @ VOMdc=0.8*VDDQ
Alert RONPd Max @ VOMdc=0.8*VDDQ
Alert RONPd Min @ VOHdc=0.95*VDDQ
Alert RONPd Max @ VOHdc=0.95*VDDQ
CT RONPd_CT Max @ VOBdc=0.2*VDDQ
CT RONPd_CT Max @ VOLdc=0.5*VDDQ
CT RONPd_CT Max @ VOMdc=0.8*VDDQ
CT RONPd_CT Max @ VOHdc=0.95*VDDQ
CT RONPu_CT Max @ VOBdc=0.2*VDDQ
CT RONPu_CT Max @ VOLdc=0.5*VDDQ
CT RONPu_CT Max @ VOMdc=0.8*VDDQ
CT RONPu_CT Max @ VOHdc=0.95*VDDQ
CT mode note
VOH Output high measurement level (single-ended)
VOL Output low measurement level (single-ended)
VOH Output high measurement level (Loopback)
VOL Output low measurement level (Loopback)
Single ended output slew rate MIN
Single ended output slew rate MAX
VOHdiff Differential output high measurement level
VOLdiff Differential output low measurement level
Differential output slew rate MIN
Differential output slew rate MAX
Rj RMS 1-UI Jitter without BUJ MAX (tTx_DQS_1UI_Rj_NoBUJ)
Dj pp 1-UI Jitter without BUJ MAX (tTx_DQS_1UI_Dj_NoBUJ)
Rj RMS N-UI jitter without BUJ MAX (tTx_DQS_NUI_Rj_NoBUJ)
Dj pp N-UI Jitter without BUJ MAX (tTx_DQS_NUI_Dj_NoBUJ)
Tx DQS Jitter Rj max note
Rj RMS 1-UI jitter without BUJ MAX (tTx_DQ_1UI_Rj_NoBUJ)
Dj pp 1-UI jitter without BUJ MAX (tTx_DQ_1UI_Dj_NoBUJ)
Rj RMS N-UI jitter without BUJ MAX (tTx_DQ_NUI_Rj_NoBUJ)
Dj pp N-UI jitter without BUJ MAX (tTx_DQ_NUI_Dj_NoBUJ)
Delay of any data lane relative to strobe lane MIN (tTx_DQS2DQ)
Delay of any data lane relative to strobe lane MAX (tTx_DQS2DQ)
Tx DQ Jitter Rj max note
Eye Height @ DQ-DQS skew 1UI MIN (TxEH_DQ_SES_1UI)
Eye Width @ DQ-DQS skew 1UI MIN (TxEW_DQ_SES_1UI)
Eye Height @ DQ-DQS skew 2UI MIN (TxEH_DQ_SES_2UI)
Eye Width @ DQ-DQS skew 2UI MIN (TxEW_DQ_SES_2UI)
Eye Height @ DQ-DQS skew 3UI MIN (TxEH_DQ_SES_3UI)
Eye Width @ DQ-DQS skew 3UI MIN (TxEW_DQ_SES_3UI)
Eye Height @ DQ-DQS skew 4UI MIN (TxEH_DQ_SES_4UI)
Eye Width @ DQ-DQS skew 4UI MIN (TxEW_DQ_SES_4UI)
Eye Height @ DQ-DQS skew 5UI MIN (TxEH_DQ_SES_5UI)
Eye Width @ DQ-DQS skew 5UI MIN (TxEW_DQ_SES_5UI)
Dimension tolerance note
Front left section width
Front right section width
Front-left edge dimension
Front-right edge dimension
Front left margin dimension
Module height (Front, right edge)
Module back dimension
Back height dimension
Back lower-left dimension
Pin reference (Detail A)
Pin reference (Detail D)
Pin reference (Detail B)
Pin reference (Detail C)
Contacts A,F width dimension
Contacts E dimension
Contacts B keep-out dimension
Contacts B keep-out note
Contacts D keep-out note
Contacts D keep-out dimension
Component callout (Registering Clock Driver)
Component callout (SPD)
Component callout (TS)
Revision date
Die base
Training (VrefDQ / VrefCA / VrefCS)
Maximum Power Saving Mode
Multi-Purpose Command
Per DRAM Addressability
Connectivity Test
Command mode support
CRC
Duty Cycle Adjuster (DCA) for Read - Global
Per Pin DCA for Read
Register port A input - command address
Register port input - chip select
Register port input - parity
Register input clock true
Register input clock complement
Register input reset
Register port A output - command address to DRAM
Register port A output - chip select 0
Register port A output - clock true/complement
Register port A output - reset
Register port A output - error in
Register port A output - loopback data
Register port A output - loopback strobe
Register port B output - command address to DRAM
Register port B output - chip select 0
Register port B output - clock true/complement
Register port B output - reset
Register port B output - error in
Register port B output - loopback data
Register port B output - loopback strobe
DRAM placement - front side row 1 (left of register)
DRAM placement - front side row 1 (right of register)
DRAM placement - back side row 2 (left)
DRAM placement - back side row 2 (right)
Note 1 - resistor value (page 1)
DRAM placement - port A DRAM group
Port A command/address bus to DRAM group
Port A DQ/DQS mapping - D0BA
Port A DQ/DQS mapping - D1FA
Port A DQ/DQS mapping - D2BA
Port A DQ/DQS mapping - D3FA
Port A DQ/DQS mapping - D4BA (ECC/CB)
DRAM placement - port B DRAM group
Port B command/address bus to DRAM group
Port B DQ/DQS mapping - D4BB (ECC/CB)
Port B DQ/DQS mapping - D5FB
Port B DQ/DQS mapping - D6BB
Port B DQ/DQS mapping - D7FB
Port B DQ/DQS mapping - D8BB
Note 1 - resistor value (page 2)
Note 2 - DRAM ZQ pin resistor
Speed Bin (DDR5-4400)
Down Bin 3200C — tAAmin / tRCDmin tRPmin / CL / tCK(AVG) min / max
Down Bin 3200BN/3200B — tAAmin / tRCD tRP / CL / tCK(AVG)
Down Bin 3200AN — tAAmin / CL
Down Bin 3600C — tAAmin / CL / tCK(AVG)
Down Bin 3600BN/3600B — tAAmin / CL / tCK(AVG)
Down Bin 3600AN — tAAmin / CL
Down Bin 4000C — tAAmin / tRCD tRP / CL / tCK(AVG)
Down Bin 4000BN/4000B — tAAmin / CL / tCK(AVG)
Down Bin 4000AN — tAAmin / CL
Down Bin 4400C — tAAmin / tRCD tRP / CL / tCK(AVG)
Down Bin 4400BN/4400B — tAAmin / CL / tCK(AVG)
Down Bin 4400AN — tAAmin / CL
Speed Bin (DDR5-4800)
Down Bin 4800C — tAAmin / CL / tCK(AVG)
Down Bin 4800BN — tAAmin / CL / tCK(AVG)
Down Bin 4800B — tAAmin / tRCD tRP / CL / tCK(AVG)
Down Bin 4800AN — tAAmin / CL
Module overall length
Module length (inner reference)
PCB height (top edge to contact reference)
Height reference
Edge/corner reference dimension
Contact area dimension (left segment)
Contact area dimension (right segment)
Contact tip reference dimension
Back-side feature dimension
Detail of Contacts A,F - contact thickness
Detail of Contacts A,F - pin number
Detail of Contacts B - pin number
Detail of Contacts C - pin number
Detail of Contacts D - keep out note
Detail of Contacts D - keep out max
Detail B - keep out note
Detail B - keep out max
Corner radius callout
Edge dimension
Tolerance note
Units note
View label
Based on die
ACT to PRE command period (max)
tRCDmin / tRPmin
Current Specification table title
Module length to notch (Front)
Front contact span dimension
Registering Clock Driver pitch
Corner radius (Front)
Contact detail width (Detail E)
Contact thickness
Contact dimension (Detail A, F)
Contact dimension (Detail E)
Detail E reference dimension
Contact dimension (Detail B)
Pin number (Detail B)
Contact dimension (Detail C)
Pin number (Detail C)
Contact dimension (Detail D)
Contact thickness (Detail D)
Keep-out area (Detail B)
Keep-out max dimension
Keep-out area (Detail D)
Keep-out max dimension (Detail D)
Component callout
Central component
Register input signals (channel A side)
Register output signals (A side)
Register output signals (B side)
DRAM site labels (front row)
DRAM site labels (back row)
Default resistor value
DRAM site labels (A-side detail, upper)
A-side data/strobe routing
DRAM site labels (B-side detail, lower)
B-side data/strobe routing
DRAM ZQ pin resistor value
Rx Mask voltage - p-p (VciVW) - DDR5-3200 Max
Rx Mask voltage - p-p (VciVW) - DDR5-3600 Max
Rx Mask voltage - p-p (VciVW) - DDR5-4000 Max
Rx Mask voltage - p-p (VciVW) - DDR5-4400 Max
Rx Mask voltage - p-p (VciVW) - DDR5-4800 Max
Rx Timing Window (TcIVW) - DDR5-3200 Max
Rx Timing Window (TcIVW) - DDR5-3600 Max
Rx Timing Window (TcIVW) - DDR5-4000 Max
Rx Timing Window (TcIVW) - DDR5-4400 Max
Rx Timing Window (TcIVW) - DDR5-4800 Max
CA Input Pulse Amplitude (VIHL_AC) - DDR5-3200
CA Input Pulse Amplitude (VIHL_AC) - DDR5-3600
CA Input Pulse Amplitude (VIHL_AC) - DDR5-4000
CA Input Pulse Amplitude (VIHL_AC) - DDR5-4400
CA Input Pulse Amplitude (VIHL_AC) - DDR5-4800
CA Input Pulse Width (TcIPW) - DDR5-3200
CA Input Pulse Width (TcIPW) - DDR5-3600
CA Input Pulse Width (TcIPW) - DDR5-4000
CA Input Pulse Width (TcIPW) - DDR5-4400
CA Input Pulse Width (TcIPW) - DDR5-4800
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3200 Min
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3200 Max
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3600 Min
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-3600 Max
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4000 Min
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4000 Max
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4400 Min
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4400 Max
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4800 Min
Input Slew Rate over VcIVW (SRIN_cIVW) - DDR5-4800 Max
DRAM Reference clock frequency (tCK) - DDR5-3200 Min
DRAM Reference clock frequency (tCK) - DDR5-3200 Max
DRAM Reference clock frequency (tCK) - DDR5-3600 Min
DRAM Reference clock frequency (tCK) - DDR5-3600 Max
DRAM Reference clock frequency (tCK) - DDR5-4000 Min
DRAM Reference clock frequency (tCK) - DDR5-4000 Max
DRAM Reference clock frequency (tCK) - DDR5-4400 Min
DRAM Reference clock frequency (tCK) - DDR5-4400 Max
DRAM Reference clock frequency (tCK) - DDR5-4800 Min
DRAM Reference clock frequency (tCK) - DDR5-4800 Max
Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-3200 Max
Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-3600 Max
Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-4000 Max
Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-4400 Max
Duty Cycle Error (tCK_Duty_UI_Error) - DDR5-4800 Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-3200 Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-3600 Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-4000 Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-4400 Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) - DDR5-4800 Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-3200 Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-3600 Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-4000 Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-4400 Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) - DDR5-4800 Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-3200 Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-3600 Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-4000 Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-4400 Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) - DDR5-4800 Max
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-3200 Max
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-3600 Max
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-4000 Max
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-4400 Max
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ (N=2,3)) - DDR5-4800 Max
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-3200 Max
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-3600 Max
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-4000 Max
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-4400 Max
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ (N=2,3)) - DDR5-4800 Max
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-3200 Max
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-3600 Max
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-4000 Max
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-4400 Max
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ (N=2,3)) - DDR5-4800 Max
Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-3200 Max
Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-3600 Max
Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-4000 Max
Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-4400 Max
Rj RMS value of N-UI Jitter, where N=4..30 (tCK_NUI_Rj_NoBUJ (N=4..30)) - DDR5-4800 Max
Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-3200 Max
Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-3600 Max
Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-4000 Max
Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-4400 Max
Dj pp value of N-UI Jitter, where N=4..30 (tCK_NUI_Dj_NoBUJ (N=4..30)) - DDR5-4800 Max
Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-3200 Max
Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-3600 Max
Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-4000 Max
Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-4400 Max
Tj value of N-UI Jitter, where N=4..30 (tCK_NUI_Tj_NoBUJ (N=4..30)) - DDR5-4800 Max
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - DDR5-3200-4800 Max
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) - DDR5-6800-8400 Max
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-3200 Max
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-3600 Max
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-4000 Max
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-4400 Max
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) - DDR5-4800 Max
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3200 Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3200 Max
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3600 Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-3600 Max
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4000 Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4000 Max
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4400 Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4400 Max
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4800 Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) - DDR5-4800 Max
DQ Timing Width (tRx_DQ_tMargin) - DDR5-3200 Min
DQ Timing Width (tRx_DQ_tMargin) - DDR5-3600 Min
DQ Timing Width (tRx_DQ_tMargin) - DDR5-4000 Min
DQ Timing Width (tRx_DQ_tMargin) - DDR5-4400 Min
DQ Timing Width (tRx_DQ_tMargin) - DDR5-4800 Min
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-3200 Max
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-3600 Max
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-4000 Max
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-4400 Max
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) - DDR5-4800 Max
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-3200 Max
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-3600 Max
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-4000 Max
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-4400 Max
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) - DDR5-4800 Max
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-3200 Max
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-3600 Max
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-4000 Max
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-4400 Max
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) - DDR5-4800 Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3200 Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3200 Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3600 Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-3600 Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4000 Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4000 Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4400 Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4400 Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4800 Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) - DDR5-4800 Max
Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-3200 Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-3200 Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-3200 Max
Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-3600 Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-3600 Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-3600 Max
Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-4000 Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-4000 Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-4000 Max
Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-4400 Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-4400 Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-4400 Max
Applied DCD to the DQS (tRx_DQS_DCD) - DDR5-4800 Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) - DDR5-4800 Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) - DDR5-4800 Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-3200 Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-3600 Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-4000 Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-4400 Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) - DDR5-4800 Max
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) - DDR5-3200-4800 Max
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3200 Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3200 Max
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3600 Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-3600 Max
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4000 Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4000 Max
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4400 Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4400 Max
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4800 Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) - DDR5-4800 Max
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-3200 Max
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-3600 Max
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-4000 Max
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) - DDR5-4400-6400 Max
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Min
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Min
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Min
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Min
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Min
Injected sinusoidal jitter at 200 MHz to meet above data eye (Sj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Min
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Min
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Min
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Min
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Min
Injected Random wide band (10 MHz-1 GHz) Jitter to meet above data eye (Rj_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Min
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3200 Max
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Min
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-3600 Max
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Min
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4000 Max
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Min
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4400 Max
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Min
Injected voltage noise as PRBS23 or at 2.1 GHz to meet above data eye (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) - DDR5-4800 Max
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3200 Min
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3200 Max
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3600 Min
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-3600 Max
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4000 Min
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4000 Max
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4400 Min
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4400 Max
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4800 Min
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) - DDR5-4800 Max
Output Driver DC Electrical Characteristics
RON34Pd Unit @ VOLdc=0.5*VDDQ
Mismatch between pull-up and pull-down MMPuPd Min @ VOMdc=0.8*VDDQ
Mismatch between pull-up and pull-down MMPuPd Max @ VOMdc=0.8*VDDQ
Mismatch DQ-DQ within byte variation pull-up MMPudd Max @ VOMdc=0.8*VDDQ
Mismatch DQ-DQ within byte variation pull-dn MMPddd Max @ VOMdc=0.8*VDDQ
Loopback Output Driver DC Electrical Characteristics
LB Mismatch between pull-up and pull-down MMPuPd Min
LB Mismatch between pull-up and pull-down MMPuPd Max
LB Mismatch LBDQS-LBDQ within device variation pull-up MMPudd Max
LB Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd Max
Loopback driver Ron support
tLBQSL Loopback LBDQS Output Low Time MIN
tLBQSH Loopback LBDQS Output High Time MIN
tLBDQSQ Loopback LBDQS to LBDQ Skew MIN
tLBQH Loopback LBDQ Output Time from LBDQS MIN
tLBDVW Loopback Data valid window MIN
Loopback Output Timing note
Alert RONPd Unit @ VOLdc=0.1*VDDQ
Alert RONPd Unit @ VOHdc=0.95*VDDQ
CT mode RONNOM
CT mode drive strength tolerance
Loopback VOH Output high measurement level (for output SR)
Loopback VOL Output low measurement level (for output SR)
Single-ended output levels note
SRQse Single ended output slew rate MIN
SRQse Single ended output slew rate MAX
Single-ended output slew rate note
Differential output levels note
SRQdiff Differential output slew rate MIN
SRQdiff Differential output slew rate MAX
Differential output slew rate note
tTx_DQS_1UI_Rj_NoBUJ Rj RMS Value of 1-UI Jitter without BUJ MAX
tTx_DQS_1UI_Dj_NoBUJ Dj pp Value of 1-UI Jitter without BUJ MAX
tTx_DQS_NUI_Rj_NoBUJ Rj RMS Value of N-UI jitter without BUJ (1<N<4) MAX
tTx_DQS_NUI_Dj_NoBUJ Dj pp Value of N-UI Jitter without BUJ (1<N<4) MAX
Tx DQS Jitter max Rj note
tTx_DQ_1UI_Rj_NoBUJ Rj RMS of 1-UI jitter without BUJ MAX
tTx_DQ_1UI_Dj_NoBUJ Dj pp 1-UI jitter without BUJ MAX
tTx_DQ_NUI_Rj_NoBUJ Rj RMS of N-UI jitter without BUJ (1<N<4) MAX
tTx_DQ_NUI_Dj_NoBUJ Dj pp N-UI jitter without BUJ (1<N<4) MAX
tTx_DQS2DQ Delay of any data lane relative to strobe lane MIN
tTx_DQS2DQ Delay of any data lane relative to strobe lane MAX
Tx DQ Jitter max Rj note
TxEH_DQ_SES_1UI Eye Height (skew DQ/DQS 1UI) MIN
TxEW_DQ_SES_1UI Eye Width (skew DQ/DQS 1UI) MIN
TxEH_DQ_SES_2UI Eye Height (skew DQ/DQS 2UI) MIN
TxEW_DQ_SES_2UI Eye Width (skew DQ/DQS 2UI) MIN
TxEH_DQ_SES_3UI Eye Height (skew DQ/DQS 3UI) MIN
TxEW_DQ_SES_3UI Eye Width (skew DQ/DQS 3UI) MIN
TxEH_DQ_SES_4UI Eye Height (skew DQ/DQS 4UI) MIN
TxEW_DQ_SES_4UI Eye Width (skew DQ/DQS 4UI) MIN
TxEH_DQ_SES_5UI Eye Height (skew DQ/DQS 5UI) MIN
TxEW_DQ_SES_5UI Eye Width (skew DQ/DQS 5UI) MIN
Tx DQ Stressed Eye BER note
Module density / configuration
Module width (overall, front top)
Module width (inner, front)
Front contacts span (left group)
Front contacts span (right group)
Contact-to-edge offset (front)
Contact-to-edge offset (front, right)
Left edge offset (front)
Module height (front, right side)
Feature height (front, right side)
Module height (back, left side)
Detail A contacts dimension
Detail E contacts dimension
Detail E offset
Detail E keep-out height
Detail B contacts dimension
Detail C contacts dimension
Detail D keep-out dimension
Detail D contacts dimension
Keep-out note (Detail with keep out)
Keep-out dimension
Detail dimension
Detail labels
Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ, Min
Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte variation pull-up MMPudd, VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte variation pull-dn MMPddd, VOMdc=0.8*VDDQ, Max
Loopback driver RON34Pd, VOLdc=0.5*VDDQ, Min
Loopback driver RON34Pd, VOLdc=0.5*VDDQ, Nom
Loopback driver RON34Pd, VOLdc=0.5*VDDQ, Max
Loopback driver RON34Pd, VOMdc=0.8*VDDQ, Min
Loopback driver RON34Pd, VOMdc=0.8*VDDQ, Nom
Loopback driver RON34Pd, VOMdc=0.8*VDDQ, Max
Loopback driver RON34Pd, VOHdc=0.95*VDDQ, Min
Loopback driver RON34Pd, VOHdc=0.95*VDDQ, Nom
Loopback driver RON34Pd, VOHdc=0.95*VDDQ, Max
Loopback driver RON34Pu, VOLdc=0.5*VDDQ, Min
Loopback driver RON34Pu, VOLdc=0.5*VDDQ, Nom
Loopback driver RON34Pu, VOLdc=0.5*VDDQ, Max
Loopback driver RON34Pu, VOMdc=0.8*VDDQ, Min
Loopback driver RON34Pu, VOMdc=0.8*VDDQ, Nom
Loopback driver RON34Pu, VOMdc=0.8*VDDQ, Max
Loopback driver RON34Pu, VOHdc=0.95*VDDQ, Min
Loopback driver RON34Pu, VOHdc=0.95*VDDQ, Nom
Loopback driver RON34Pu, VOHdc=0.95*VDDQ, Max
Loopback Mismatch between pull-up and pull-down MMPuPd, Min
Loopback Mismatch between pull-up and pull-down MMPuPd, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd, Max
Loopback LBDQS Output Low Time tLBQSL, DDR5-3200, MIN
Loopback LBDQS Output Low Time tLBQSL, DDR5-3600, MIN
Loopback LBDQS Output Low Time tLBQSL, DDR5-4000, MIN
Loopback LBDQS Output Low Time tLBQSL, DDR5-4400, MIN
Loopback LBDQS Output Low Time tLBQSL, DDR5-4800, MIN
Loopback LBDQS Output High Time tLBQSH, DDR5-3200, MIN
Loopback LBDQS Output High Time tLBQSH, DDR5-3600, MIN
Loopback LBDQS Output High Time tLBQSH, DDR5-4000, MIN
Loopback LBDQS Output High Time tLBQSH, DDR5-4400, MIN
Loopback LBDQS Output High Time tLBQSH, DDR5-4800, MIN
Loopback LBDQS to LBDQ Skew tLBDQSQ, DDR5-3200, MIN
Loopback LBDQS to LBDQ Skew tLBDQSQ, DDR5-3600, MIN
Loopback LBDQS to LBDQ Skew tLBDQSQ, DDR5-4000, MIN
Loopback LBDQS to LBDQ Skew tLBDQSQ, DDR5-4400, MIN
Loopback LBDQS to LBDQ Skew tLBDQSQ, DDR5-4800, MIN
Loopback LBDQ Output Time from LBDQS tLBQH, DDR5-3200, MIN
Loopback LBDQ Output Time from LBDQS tLBQH, DDR5-3600, MIN
Loopback LBDQ Output Time from LBDQS tLBQH, DDR5-4000, MIN
Loopback LBDQ Output Time from LBDQS tLBQH, DDR5-4400, MIN
Loopback LBDQ Output Time from LBDQS tLBQH, DDR5-4800, MIN
Loopback Data valid window tLBDVW, DDR5-3200, MIN
Loopback Data valid window tLBDVW, DDR5-3600, MIN
Loopback Data valid window tLBDVW, DDR5-4000, MIN
Loopback Data valid window tLBDVW, DDR5-4400, MIN
Loopback Data valid window tLBDVW, DDR5-4800, MIN
Alert_n RONPd, VOLdc=0.1*VDDQ, Min
Alert_n RONPd, VOLdc=0.1*VDDQ, Max
Alert_n RONPd, VOMdc=0.8*VDDQ, Min
Alert_n RONPd, VOMdc=0.8*VDDQ, Max
Alert_n RONPd, VOHdc=0.95*VDDQ, Min
Alert_n RONPd, VOHdc=0.95*VDDQ, Max
Connectivity Test (CT) Mode RONPd_CT, VOBdc=0.2xVDDQ, Max
Connectivity Test (CT) Mode RONPd_CT, VOLdc=0.5xVDDQ, Max
Connectivity Test (CT) Mode RONPd_CT, VOMdc=0.8xVDDQ, Max
Connectivity Test (CT) Mode RONPd_CT, VOHdc=0.95xVDDQ, Max
Connectivity Test (CT) Mode RONPu_CT, VOBdc=0.2xVDDQ, Max
Connectivity Test (CT) Mode RONPu_CT, VOLdc=0.5xVDDQ, Max
Connectivity Test (CT) Mode RONPu_CT, VOMdc=0.8xVDDQ, Max
Connectivity Test (CT) Mode RONPu_CT, VOHdc=0.95xVDDQ, Max
Single-ended Output high measurement level VOH for Loopback Signals, DDR5-3200-6400
Single-ended Output low measurement level VOL for Loopback Signals, DDR5-3200-6400
Single ended output slew rate SRQse, DDR5-3200, MIN
Single ended output slew rate SRQse, DDR5-3200, MAX
Single ended output slew rate SRQse, DDR5-3600, MIN
Single ended output slew rate SRQse, DDR5-3600, MAX
Single ended output slew rate SRQse, DDR5-4000, MIN
Single ended output slew rate SRQse, DDR5-4000, MAX
Single ended output slew rate SRQse, DDR5-4400, MIN
Single ended output slew rate SRQse, DDR5-4400, MAX
Single ended output slew rate SRQse, DDR5-4800, MIN
Single ended output slew rate SRQse, DDR5-4800, MAX
Differential output high measurement level VOHdiff (for output SR), DDR5-3200-6400
Differential output low measurement level VOLdiff (for output SR), DDR5-3200-6400
Differential output slew rate SRQdiff, DDR5-3200, MIN
Differential output slew rate SRQdiff, DDR5-3200, MAX
Differential output slew rate SRQdiff, DDR5-3600, MIN
Differential output slew rate SRQdiff, DDR5-3600, MAX
Differential output slew rate SRQdiff, DDR5-4000, MIN
Differential output slew rate SRQdiff, DDR5-4000, MAX
Differential output slew rate SRQdiff, DDR5-4400, MIN
Differential output slew rate SRQdiff, DDR5-4400, MAX
Differential output slew rate SRQdiff, DDR5-4800, MIN
Differential output slew rate SRQdiff, DDR5-4800, MAX
Tx DQS Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ, DDR5-3200, MAX
Tx DQS Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ, DDR5-3600, MAX
Tx DQS Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ, DDR5-4000, MAX
Tx DQS Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ, DDR5-4400, MAX
Tx DQS Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ, DDR5-4800, MAX
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ, DDR5-3200, MAX
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ, DDR5-3600, MAX
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ, DDR5-4000, MAX
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ, DDR5-4400, MAX
Tx DQS Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ, DDR5-4800, MAX
Tx DQS Rj RMS Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Rj_NoBUJ, MAX
Tx DQS Rj RMS Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Rj_NoBUJ, MAX
Tx DQ Rj RMS of 1-UI jitter without BUJ tTx_DQ_1UI_Rj_NoBUJ, MAX
Tx DQ Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ, DDR5-3200, MAX
Tx DQ Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ, DDR5-3600, MAX
Tx DQ Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ, DDR5-4000, MAX
Tx DQ Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ, DDR5-4400, MAX
Tx DQ Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ, DDR5-4800, MAX
Tx DQ Rj RMS of N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Rj_NoBUJ, MAX
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ, DDR5-3200, MAX
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ, DDR5-3600, MAX
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ, DDR5-4000, MAX
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ, DDR5-4400, MAX
Tx DQ Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ, DDR5-4800, MAX
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-3200, MIN
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-3200, MAX
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-3600, MIN
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-3600, MAX
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-4000, MIN
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-4000, MAX
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-4400, MIN
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-4400, MAX
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-4800, MIN
Tx DQ Delay of any data lane relative to strobe lane tTx_DQS2DQ, DDR5-4800, MAX
Tx DQ Stressed Eye Width TxEW_DQ_SES_1UI (skew DQ-DQS 1UI), DDR5-3200, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_1UI (skew DQ-DQS 1UI), DDR5-3600, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_1UI (skew DQ-DQS 1UI), DDR5-4000, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_1UI (skew DQ-DQS 1UI), DDR5-4400, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_1UI (skew DQ-DQS 1UI), DDR5-4800, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_2UI (skew DQ-DQS 2UI), DDR5-3200, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_2UI (skew DQ-DQS 2UI), DDR5-3600, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_2UI (skew DQ-DQS 2UI), DDR5-4000, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_2UI (skew DQ-DQS 2UI), DDR5-4400, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_2UI (skew DQ-DQS 2UI), DDR5-4800, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_3UI (skew DQ-DQS 3UI), DDR5-3200, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_3UI (skew DQ-DQS 3UI), DDR5-3600, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_3UI (skew DQ-DQS 3UI), DDR5-4000, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_3UI (skew DQ-DQS 3UI), DDR5-4400, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_3UI (skew DQ-DQS 3UI), DDR5-4800, MIN
Tx DQ Stressed Eye Height TxEH_DQ_SES_1UI (skew DQ-DQS 1UI), DDR5-3200..4800, MIN
Tx DQ Stressed Eye Height TxEH_DQ_SES_2UI (skew DQ-DQS 2UI), DDR5-3200..4800, MIN
Tx DQ Stressed Eye Height TxEH_DQ_SES_3UI (skew DQ-DQS 3UI), DDR5-3200..4800, MIN
Tx DQ Stressed Eye Height TxEH_DQ_SES_4UI (skew DQ-DQS 4UI), DDR5-3200..4800, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_4UI (skew DQ-DQS 4UI), DDR5-3200..4800, MIN
Tx DQ Stressed Eye Height TxEH_DQ_SES_5UI (skew DQ-DQS 5UI), DDR5-3200..4800, MIN
Tx DQ Stressed Eye Width TxEW_DQ_SES_5UI (skew DQ-DQS 5UI), DDR5-3200..4800, MIN
Connectivity Test mode uncalibrated drive strength tolerance
Supported Frequency Down Bin 3200C tAAmin/tRCDmin/tRPmin
Supported Frequency Down Bin (15.000 row, RESERVED tCK)
Module current basis note
Module width dimension (Front)
Front view dimension
Contact group span dimension (Front)
Registering Clock Driver callout (Front)
Module height (Front, right side)
Detail labels (Front)
Back view dimension
Side view thickness
Side view label
Detail of Contacts A, F dimension
Detail of Contacts A, F radius
Detail of Contacts A, F pin reference
Detail of Contacts B pin reference
Detail of Contacts C pin reference
Detail of Contacts D keep out area note
Detail E keep out area note
Detail A component callout
Application
Central control component
DRAM device placement - front row
DRAM device placement - back row
A-side DRAM device placement
A-side data byte-lane assignments
A-side register output net
B-side DRAM device placement
B-side data byte-lane assignments
B-side register output net
VDD - Voltage on VDD pin relative to Vss (Absolute Maximum Rating)
VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Maximum Rating)
VPP - Voltage on VPP pin relative to Vss (Absolute Maximum Rating)
VIN, VOUT - Voltage on any pin relative to Vss (Absolute Maximum Rating)
TSTG - Storage Temperature (Absolute Maximum Rating)
VDD - Z(f) Spec (Freq: 2MHz to 10MHz), Zmax
VDD - Z(f) Spec (Freq: 20MHz), Zmax
VDDQ - Z(f) Spec (Freq: 2MHz to 10MHz), Zmax
VDDQ - Z(f) Spec (Freq: 20MHz), Zmax
VPP - Z(f) Spec (Freq: 2MHz to 10MHz), Zmax
VPP - Z(f) Spec (Freq: 20MHz), Zmax
Loopback Mismatch MMPuPd, VOMdc=0.8*VDDQ, Min
Loopback Mismatch MMPuPd, VOMdc=0.8*VDDQ, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd, VOMdc=0.8*VDDQ, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd, VOMdc=0.8*VDDQ, Max
tLBQSL Loopback LBDQS Output Low Time, DDR5-3200, MIN
tLBQSL Loopback LBDQS Output Low Time, DDR5-3600, MIN
tLBQSL Loopback LBDQS Output Low Time, DDR5-4000, MIN
tLBQSL Loopback LBDQS Output Low Time, DDR5-4400, MIN
tLBQSL Loopback LBDQS Output Low Time, DDR5-4800, MIN
tLBQSH Loopback LBDQS Output High Time, DDR5-3200, MIN
tLBQSH Loopback LBDQS Output High Time, DDR5-3600, MIN
tLBQSH Loopback LBDQS Output High Time, DDR5-4000, MIN
tLBQSH Loopback LBDQS Output High Time, DDR5-4400, MIN
tLBQSH Loopback LBDQS Output High Time, DDR5-4800, MIN
tLBDQSQ Loopback LBDQS to LBDQ Skew, DDR5-3200, MIN
tLBDQSQ Loopback LBDQS to LBDQ Skew, DDR5-3600, MIN
tLBDQSQ Loopback LBDQS to LBDQ Skew, DDR5-4000, MIN
tLBDQSQ Loopback LBDQS to LBDQ Skew, DDR5-4400, MIN
tLBDQSQ Loopback LBDQS to LBDQ Skew, DDR5-4800, MIN
tLBQH Loopback LBDQ Output Time from LBDQS, DDR5-3200, MIN
tLBQH Loopback LBDQ Output Time from LBDQS, DDR5-3600, MIN
tLBQH Loopback LBDQ Output Time from LBDQS, DDR5-4000, MIN
tLBQH Loopback LBDQ Output Time from LBDQS, DDR5-4400, MIN
tLBQH Loopback LBDQ Output Time from LBDQS, DDR5-4800, MIN
tLBDVW Loopback Data valid window, DDR5-3200, MIN
tLBDVW Loopback Data valid window, DDR5-3600, MIN
tLBDVW Loopback Data valid window, DDR5-4000, MIN
tLBDVW Loopback Data valid window, DDR5-4400, MIN
tLBDVW Loopback Data valid window, DDR5-4800, MIN
Single-ended VOH Output high measurement level (for output SR), DDR5-3200-6400
Single-ended VOL Output low measurement level (for output SR), DDR5-3200-6400
Loopback Single-ended VOH Output high measurement level (for output SR), DDR5-3200-6400
Loopback Single-ended VOL Output low measurement level (for output SR), DDR5-3200-6400
SRQse Single ended output slew rate, DDR5-3200, MIN
SRQse Single ended output slew rate, DDR5-3200, MAX
SRQse Single ended output slew rate, DDR5-3600, MIN
SRQse Single ended output slew rate, DDR5-3600, MAX
SRQse Single ended output slew rate, DDR5-4000, MIN
SRQse Single ended output slew rate, DDR5-4000, MAX
SRQse Single ended output slew rate, DDR5-4400, MIN
SRQse Single ended output slew rate, DDR5-4400, MAX
SRQse Single ended output slew rate, DDR5-4800, MIN
SRQse Single ended output slew rate, DDR5-4800, MAX
VOHdiff Differential output high measurement level (for output SR), DDR5-3200-6400
VOLdiff Differential output low measurement level (for output SR), DDR5-3200-6400
SRQdiff Differential output slew rate, DDR5-3200, MIN
SRQdiff Differential output slew rate, DDR5-3200, MAX
SRQdiff Differential output slew rate, DDR5-3600, MIN
SRQdiff Differential output slew rate, DDR5-3600, MAX
SRQdiff Differential output slew rate, DDR5-4000, MIN
SRQdiff Differential output slew rate, DDR5-4000, MAX
SRQdiff Differential output slew rate, DDR5-4400, MIN
SRQdiff Differential output slew rate, DDR5-4400, MAX
SRQdiff Differential output slew rate, DDR5-4800, MIN
SRQdiff Differential output slew rate, DDR5-4800, MAX
Supported Frequency Down Bin 3200C - tAAmin
Supported Frequency Down Bin 3200C - Read CL Write CWL
Supported Frequency Down Bin 3200C - tCK(AVG) min
Supported Frequency Down Bin 3200C - tCK(AVG) max
Supported Frequency Down Bin 3200BN/3200B - tAAmin
Supported Frequency Down Bin 3200BN/3200B - tRCDmin/tRPmin
Supported Frequency Down Bin 3200BN/3200B - Read CL Write CWL
Supported Frequency Down Bin 3200BN/3200B - tCK(AVG) min
Supported Frequency Down Bin 3200BN/3200B - tCK(AVG) max
Supported Frequency Down Bin 3200AN - tAAmin
Supported Frequency Down Bin 3200AN - tRCDmin/tRPmin
Supported Frequency Down Bin 3200AN - Read CL Write CWL
Supported Frequency Down Bin 3200AN - tCK(AVG)
Supported Frequency Down Bin (RESERVED row near 3200) - tAAmin
Supported Frequency Down Bin (RESERVED row near 3200) - Read CL Write CWL
Supported Frequency Down Bin 3600C - tAAmin
Supported Frequency Down Bin 3600C - tRCDmin/tRPmin
Supported Frequency Down Bin 3600C - Read CL Write CWL
Supported Frequency Down Bin 3600C - tCK(AVG) min
Supported Frequency Down Bin 3600C - tCK(AVG) max
Supported Frequency Down Bin 3600BN/3600B - tAAmin
Supported Frequency Down Bin 3600BN/3600B - tRCDmin/tRPmin
Supported Frequency Down Bin 3600BN/3600B - Read CL Write CWL
Supported Frequency Down Bin 3600BN/3600B - tCK(AVG) min
Supported Frequency Down Bin 3600BN/3600B - tCK(AVG) max
Supported Frequency Down Bin 3600AN - tAAmin
Supported Frequency Down Bin 3600AN - tRCDmin/tRPmin
Supported Frequency Down Bin 3600AN - Read CL Write CWL
Supported Frequency Down Bin 3600AN - tCK(AVG)
Supported Frequency Down Bin 4000C - tAAmin
Supported Frequency Down Bin 4000C - tRCDmin/tRPmin
Supported Frequency Down Bin 4000C - Read CL Write CWL
Supported Frequency Down Bin 4000C - tCK(AVG) min
Supported Frequency Down Bin 4000C - tCK(AVG) max
Supported Frequency Down Bin 4000BN/4000B - tAAmin
Supported Frequency Down Bin 4000BN/4000B - tRCDmin/tRPmin
Supported Frequency Down Bin 4000BN/4000B - Read CL Write CWL
Supported Frequency Down Bin 4000BN/4000B - tCK(AVG) min
Supported Frequency Down Bin 4000BN/4000B - tCK(AVG) max
Supported Frequency Down Bin 4000AN - tAAmin
Supported Frequency Down Bin 4000AN - tRCDmin/tRPmin
Supported Frequency Down Bin 4000AN - Read CL Write CWL
Supported Frequency Down Bin 4000AN - tCK(AVG)
Supported Frequency Down Bin 4400C - tAAmin
Supported Frequency Down Bin 4400C - tRCDmin/tRPmin
Supported Frequency Down Bin 4400C - Read CL Write CWL
Supported Frequency Down Bin 4400C - tCK(AVG) min
Supported Frequency Down Bin 4400C - tCK(AVG) max
Supported Frequency Down Bin 4400BN/4400B - tAAmin
Supported Frequency Down Bin 4400BN/4400B - tRCDmin/tRPmin
Supported Frequency Down Bin 4400BN/4400B - Read CL Write CWL
Supported Frequency Down Bin 4400BN/4400B - tCK(AVG) min
Supported Frequency Down Bin 4400BN/4400B - tCK(AVG) max
Supported Frequency Down Bin 4400AN - tAAmin
Supported Frequency Down Bin 4400AN - tRCDmin/tRPmin
Supported Frequency Down Bin 4400AN - Read CL Write CWL
Supported Frequency Down Bin 4400AN - tCK(AVG)
Internal read command to first data (tAA) DDR5-4800B
ACT to internal read or write delay time (tRCD) DDR5-4800B
Row Precharge Time (tRP) DDR5-4800B
ACT to PRE command period (tRAS) DDR5-4800B min
ACT to PRE command period (tRAS) DDR5-4800B max
ACT to ACT or REF command period (tRC) DDR5-4800B
CAS Write Latency (CWL) DDR5-4800B
Supported Frequency Down Bin 4800C - tAAmin
Supported Frequency Down Bin 4800C - tRCDmin/tRPmin
Supported Frequency Down Bin 4800C - Read CL Write CWL
Supported Frequency Down Bin 4800C - tCK(AVG) min
Supported Frequency Down Bin 4800C - tCK(AVG) max
Supported Frequency Down Bin 4800BN - tAAmin
Supported Frequency Down Bin 4800BN - tRCDmin/tRPmin
Supported Frequency Down Bin 4800BN - Read CL Write CWL
Supported Frequency Down Bin 4800BN - tCK(AVG) min
Supported Frequency Down Bin 4800BN - tCK(AVG) max
Supported Frequency Down Bin 4800B - tAAmin
Supported Frequency Down Bin 4800B - tRCDmin/tRPmin
Supported Frequency Down Bin 4800B - Read CL Write CWL
Supported Frequency Down Bin 4800B - tCK(AVG) min
Supported Frequency Down Bin 4800B - tCK(AVG) max
Supported Frequency Down Bin 4800AN - tAAmin
Supported Frequency Down Bin 4800AN - tRCDmin/tRPmin
Supported Frequency Down Bin 4800AN - Read CL Write CWL
Supported Frequency Down Bin 4800AN - tCK(AVG)
Module width (Front overall)
Front secondary width dimension
Front dimension 2.10
Front contact span left
Front contact span right
Front detail callout
Component label (Front)
Back edge dimension
Back corner radius
Back dimension 14.60
Side dimension max
Contacts A/F dimension
Contacts A/F pin
Contacts B pin
Contacts C pin
Contacts D max dimension
Contacts E label
Contacts E pin
Contacts keep-out note
Component label (Side)
Bank count (x4/x8)
Bank count (x16)
Bank Groups (x4/x8/x16)
Diagram type
Module configuration title
Register output signal (side A)
Register output signal (side B)
DRAM placement (top routing row)
DRAM placement (bottom routing row)
Diagram note (resistor value)
DRAM placement (side A row)
Command/address bus (side A)
Data byte assignment (side A)
DRAM placement (side B row)
Command/address bus (side B)
Data byte assignment (side B)
Diagram note (ZQ resistor)
VDD - Voltage on VDD pin relative to Vss (Absolute Maximum)
VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Maximum)
VPP - Voltage on VPP pin relative to Vss (Absolute Maximum)
VIN, VOUT - Voltage on any pin relative to Vss (Absolute Maximum)
TSTG - Storage Temperature (Absolute Maximum)
VDD Z(f) Zmax 2MHz-10MHz
VDD Z(f) Zmax 20MHz
VDDQ Z(f) Zmax 2MHz-10MHz
VDDQ Z(f) Zmax 20MHz
VPP Z(f) Zmax 2MHz-10MHz
VPP Z(f) Zmax 20MHz
VcIVW Rx Mask voltage p-p (Max)
TcIVW Rx Timing Window (Max)
VIHL_AC CA Input Pulse Amplitude (3200/3600/4000)
VIHL_AC CA Input Pulse Amplitude (4400/4800)
TcIPW CA Input Pulse Width
SRIN_cIVW Input Slew Rate over VcIVW - Min
SRIN_cIVW Input Slew Rate over VcIVW - Max
tCK DRAM Reference clock frequency - Min
tCK DRAM Reference clock frequency - Max
tCK_Duty_UI_Error Duty Cycle Error (Max)
tCK_1UI_Rj_NoBUJ Rj RMS value of 1-UI Jitter (Max)
tCK_1UI_Dj_NoBUJ Dj pp value of 1-UI Jitter (Max)
tCK_1UI_Tj_NoBUJ Tj value of 1-UI Jitter (Max)
tCK_NUI_Rj_NoBUJ Rj RMS value of N-UI Jitter (N=2,3) (Max)
tCK_NUI_Dj_NoBUJ Dj pp value of N-UI Jitter (N=2,3) (Max)
tCK_NUI_Tj_NoBUJ Tj value of N-UI Jitter (N=2,3) (Max)
tCK_NUI_Rj_NoBUJ Rj RMS value of N-UI Jitter (N=4..30) (Max)
tCK_NUI_Dj_NoBUJ Dj pp value of N-UI Jitter (N=4..30) (Max)
tCK_NUI_Tj_NoBUJ Tj value of N-UI Jitter (N=4..30) (Max)
VIX_CK_Ratio Clock differential input crosspoint voltage ratio (Max, 3200-4800)
VIX_CK_Ratio Clock differential input crosspoint voltage ratio (Max, 6800-8400)
VRx_CK Input Clock Voltage Sensitivity (differential pp) - DDR5-3200 (Max)
VRx_CK Input Clock Voltage Sensitivity (differential pp) - DDR5-3600 (Max)
VRx_CK Input Clock Voltage Sensitivity (differential pp) - DDR5-4000 (Max)
VRx_CK Input Clock Voltage Sensitivity (differential pp) - DDR5-4400 (Max)
VRx_CK Input Clock Voltage Sensitivity (differential pp) - DDR5-4800 (Max)
SRIdiff_CK Differential Input Slew Rate for CK_t, CK_c - Min
SRIdiff_CK Differential Input Slew Rate for CK_t, CK_c - Max
tRx_DQ_tMargin DQ Timing Width - DDR5-3200 (Min)
tRx_DQ_tMargin DQ Timing Width - DDR5-3600 (Min)
tRx_DQ_tMargin DQ Timing Width - DDR5-4000 (Min)
tRx_DQ_tMargin DQ Timing Width - DDR5-4400 (Min)
tRx_DQ_tMargin DQ Timing Width - DDR5-4800 (Min)
ΔtRx_DQ_tMargin_DQS_DCD Degradation with DCD injection in DQS (Max)
ΔtRx_DQ_tMargin_DQS_Rj Degradation with Rj injection in DQS (Max)
ΔtRx_DQ_tMargin_DQS_DCD_Rj Degradation with DCD and Rj injection in DQS (Max)
tRx_DQS2DQ Delay of any data lane relative to DQS_t/DQS_c crossing - Min
tRx_DQS2DQ - DDR5-3200/3600/4000 (Max)
tRx_DQS2DQ - DDR5-4400 (Max)
tRx_DQS2DQ - DDR5-4800 (Max)
tRx_DQS_DCD Applied DCD to the DQS (Max)
tRx_DQS_Rj Applied Rj RMS to the DQS (Max)
tRx_DQS_DCD_Rj Applied DCD and Rj RMS to the DQS (Max)
VRx_DQS DQS Rx Input Voltage Sensitivity (differential pp) - DDR5-3200 (Max)
VRx_DQS DQS Rx Input Voltage Sensitivity (differential pp) - DDR5-3600 (Max)
VRx_DQS DQS Rx Input Voltage Sensitivity (differential pp) - DDR5-4000 (Max)
VRx_DQS DQS Rx Input Voltage Sensitivity (differential pp) - DDR5-4400 (Max)
VRx_DQS DQS Rx Input Voltage Sensitivity (differential pp) - DDR5-4800 (Max)
VIX_DQS_Ratio DQS differential input crosspoint voltage ratio (Max)
SRIdiff_DQS Differential Input Slew Rate for DQS_t, DQS_c
VRx_DQ Minimum DQ Rx input voltage sensitivity applied around Vref - DDR5-3200 (Max)
VRx_DQ Minimum DQ Rx input voltage sensitivity - DDR5-3600 (Max)
VRx_DQ Minimum DQ Rx input voltage sensitivity - DDR5-4000 (Max)
VRx_DQ Minimum DQ Rx input voltage sensitivity - DDR5-4400-6400 (Max)
RxEH_Stressed_Eye Eye height of stressed eye for Golden Reference Channel 1 - DDR5-3200 (Max)
RxEH_Stressed_Eye Eye height - DDR5-3600 (Max)
RxEH_Stressed_Eye Eye height - DDR5-4000 (Max)
RxEH_Stressed_Eye Eye height - DDR5-4400 (Max)
RxEH_Stressed_Eye Eye height - DDR5-4800 (Max)
RxEW_Stressed_Eye Eye width of stressed eye Golden Reference Channel 1 (Max)
Vswing_Stressed_Eye Vswing stress to meet above data eye (Max)
Sj_Stressed_Eye Injected sinusoidal jitter at 200 MHz - Min
Sj_Stressed_Eye Injected sinusoidal jitter at 200 MHz - Max
Rj_Stressed_Eye Injected Random wide band (10 MHz-1 GHz) Jitter - Min
Rj_Stressed_Eye Injected Random wide band (10 MHz-1 GHz) Jitter - Max
Vnoise_Stressed_Eye Injected voltage noise (PRBS23 or 2.1 GHz) - Min
Vnoise_Stressed_Eye Injected voltage noise (PRBS23 or 2.1 GHz) - Max
tCT_IS Connectivity Test Mode AC parameter - Min
tCT_Enable Connectivity Test Mode AC parameter - Min
tCT_Valid Connectivity Test Mode AC parameter - Max
CT Mode input level - TEN pin
CT Mode input level - CS_n
CT Mode input level - Test Input pins
CT Mode input level - RESET_n
TEN AC Input High Voltage VIH(AC)_TEN (Min)
TEN AC Input High Voltage VIH(AC)_TEN (Max)
TEN DC Input High Voltage VIH(DC)_TEN (Min)
TEN DC Input High Voltage VIH(DC)_TEN (Max)
TEN DC Input Low Voltage VIL(DC)_TEN (Min)
TEN DC Input Low Voltage VIL(DC)_TEN (Max)
TEN AC Input Low Voltage VIL(AC)_TEN (Min)
TEN AC Input Low Voltage VIL(AC)_TEN (Max)
TEN Input signal Falling time TF_input_TEN (Max)
TEN Input signal Rising time TR_input_TEN (Max)
RESET_n AC Input High Voltage VIH(AC)_RESET (Min)
RESET_n AC Input High Voltage VIH(AC)_RESET (Max)
RESET_n DC Input High Voltage VIH(DC)_RESET (Min)
RESET_n DC Input High Voltage VIH(DC)_RESET (Max)
RESET_n DC Input Low Voltage VIL(DC)_RESET (Min)
RESET_n DC Input Low Voltage VIL(DC)_RESET (Max)
RESET_n AC Input Low Voltage VIL(AC)_RESET (Min)
RESET_n AC Input Low Voltage VIL(AC)_RESET (Max)
RESET_n Rising time TR_RESET (Max)
RESET pulse width tPW_RESET (Min)
RON34Pd VOLdc=0.5*VDDQ (Min)
RON34Pd VOLdc=0.5*VDDQ (Nom)
RON34Pd VOLdc=0.5*VDDQ (Max)
RON34Pd VOMdc=0.8*VDDQ (Min)
RON34Pd VOMdc=0.8*VDDQ (Nom)
RON34Pd VOMdc=0.8*VDDQ (Max)
RON34Pd VOHdc=0.95*VDDQ (Min)
RON34Pd VOHdc=0.95*VDDQ (Nom)
RON34Pd VOHdc=0.95*VDDQ (Max)
RON34Pu VOLdc=0.5*VDDQ (Min)
RON34Pu VOLdc=0.5*VDDQ (Nom)
RON34Pu VOLdc=0.5*VDDQ (Max)
RON34Pu VOMdc=0.8*VDDQ (Min)
RON34Pu VOMdc=0.8*VDDQ (Nom)
RON34Pu VOMdc=0.8*VDDQ (Max)
RON34Pu VOHdc=0.95*VDDQ (Min)
RON34Pu VOHdc=0.95*VDDQ (Nom)
RON34Pu VOHdc=0.95*VDDQ (Max)
RON48Pd VOLdc=0.5*VDDQ (Min)
RON48Pd VOLdc=0.5*VDDQ (Nom)
RON48Pd VOLdc=0.5*VDDQ (Max)
RON48Pd VOMdc=0.8*VDDQ (Min)
RON48Pd VOMdc=0.8*VDDQ (Nom)
RON48Pd VOMdc=0.8*VDDQ (Max)
RON48Pd VOHdc=0.95*VDDQ (Min)
RON48Pd VOHdc=0.95*VDDQ (Nom)
RON48Pd VOHdc=0.95*VDDQ (Max)
RON48Pu VOLdc=0.5*VDDQ (Min)
RON48Pu VOLdc=0.5*VDDQ (Nom)
RON48Pu VOLdc=0.5*VDDQ (Max)
RON48Pu VOMdc=0.8*VDDQ (Min)
RON48Pu VOMdc=0.8*VDDQ (Nom)
RON48Pu VOMdc=0.8*VDDQ (Max)
RON48Pu VOHdc=0.95*VDDQ (Min)
RON48Pu VOHdc=0.95*VDDQ (Nom)
RON48Pu VOHdc=0.95*VDDQ (Max)
Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ (Min)
Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ (Max)
Mismatch DQ-DQ within byte variation pull-up MMPudd, VOMdc=0.8*VDDQ (Max)
Mismatch DQ-DQ within byte variation pull-dn MMPddd, VOMdc=0.8*VDDQ (Max)
Loopback RON34Pd VOLdc=0.5*VDDQ (Min)
Loopback RON34Pd VOLdc=0.5*VDDQ (Nom)
Loopback RON34Pd VOLdc=0.5*VDDQ (Max)
Loopback RON34Pd VOMdc=0.8*VDDQ (Min)
Loopback RON34Pd VOMdc=0.8*VDDQ (Nom)
Loopback RON34Pd VOMdc=0.8*VDDQ (Max)
Loopback RON34Pd VOHdc=0.95*VDDQ (Min)
Loopback RON34Pd VOHdc=0.95*VDDQ (Nom)
Loopback RON34Pd VOHdc=0.95*VDDQ (Max)
Loopback RON34Pu VOLdc=0.5*VDDQ (Min)
Loopback RON34Pu VOLdc=0.5*VDDQ (Nom)
Loopback RON34Pu VOLdc=0.5*VDDQ (Max)
Loopback RON34Pu VOMdc=0.8*VDDQ (Min)
Loopback RON34Pu VOMdc=0.8*VDDQ (Nom)
Loopback RON34Pu VOMdc=0.8*VDDQ (Max)
Loopback RON34Pu VOHdc=0.95*VDDQ (Min)
Loopback RON34Pu VOHdc=0.95*VDDQ (Nom)
Loopback RON34Pu VOHdc=0.95*VDDQ (Max)
Loopback Mismatch between pull-up and pull-down MMPuPd (Min)
Loopback Mismatch between pull-up and pull-down MMPuPd (Max)
Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd (Max)
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd (Max)
Loopback LBDQS Output Low Time tLBQSL (Min) DDR5-3200
Loopback LBDQS Output High Time tLBQSH (Min) DDR5-3200
Loopback LBDQS to LBDQ Skew tLBDQSQ (Min) DDR5-3200
Loopback LBDQ Output Time from LBDQS tLBQH (Min) DDR5-3200
Loopback Data valid window (tLBQH-tLBDQSQ) tLBDVW (Min) DDR5-3200
Alert_n RONPd VOLdc=0.1*VDDQ (Min)
Alert_n RONPd VOLdc=0.1*VDDQ (Max)
Alert_n RONPd VOMdc=0.8*VDDQ (Min)
Alert_n RONPd VOMdc=0.8*VDDQ (Max)
Alert_n RONPd VOHdc=0.95*VDDQ (Min)
Alert_n RONPd VOHdc=0.95*VDDQ (Max)
CT Mode RONPu_CT VOBdc=0.2xVDDQ (Max)
CT Mode RONPu_CT VOLdc=0.5xVDDQ (Max)
CT Mode RONPu_CT VOMdc=0.8xVDDQ (Max)
CT Mode RONPu_CT VOHdc=0.95xVDDQ (Max)
Single ended output slew rate SRQse (Min) DDR5-3200
Single ended output slew rate SRQse (Max) DDR5-3200
Differential output slew rate SRQdiff (Min) DDR5-3200
Differential output slew rate SRQdiff (Max) DDR5-3200
Rj RMS Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Rj_NoBUJ (Max)
Dj pp Value of 1-UI Jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ (Max)
Rj RMS Value of N-UI jitter without BUJ (1<N<4) tTx_DQS_NUI_Rj_NoBUJ (Max)
Dj pp Value of N-UI Jitter without BUJ (1<N<4) tTx_DQS_NUI_Dj_NoBUJ (Max)
Rj RMS of 1-UI jitter without BUJ tTx_DQ_1UI_Rj_NoBUJ (Max)
Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ (Max)
Rj RMS of N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Rj_NoBUJ (Max)
Dj pp N-UI jitter without BUJ (1<N<4) tTx_DQ_NUI_Dj_NoBUJ (Max)
Delay of any data lane relative to strobe lane tTx_DQS2DQ (Min)
Delay of any data lane relative to strobe lane tTx_DQS2DQ (Max)
Eye Height at transmitter, DQ/DQS skew 1UI TxEH_DQ_SES_1UI (Min)
Eye Width at transmitter, DQ/DQS skew 1UI TxEW_DQ_SES_1UI (Min)
Eye Height at transmitter, DQ/DQS skew 2UI TxEH_DQ_SES_2UI (Min)
Eye Width at transmitter, DQ/DQS skew 2UI TxEW_DQ_SES_2UI (Min)
Eye Height at transmitter, DQ/DQS skew 3UI TxEH_DQ_SES_3UI (Min)
Eye Width at transmitter, DQ/DQS skew 3UI TxEW_DQ_SES_3UI (Min)
Eye Height at transmitter, DQ/DQS skew 4UI TxEH_DQ_SES_4UI (Min)
Eye Width at transmitter, DQ/DQS skew 4UI TxEW_DQ_SES_4UI (Min)
Eye Height at transmitter, DQ/DQS skew 5UI TxEH_DQ_SES_5UI (Min)
Eye Width at transmitter, DQ/DQS skew 5UI TxEW_DQ_SES_5UI (Min)
Module length (overall, Front)
Module length (datum, Front)
Front edge offset to first contact group
Front dimension
Back dimension
PCB thickness (Side)
Detail A height
Detail F - dimension
Contact callout
tREFI1 REFab Normal, 0C<=TCASE<=85C (rREFI)
tREFI1 REFab Normal, 85C<TCASE<=95C (rREFI/2)
tREFI2 REFab Fine Granularity, 0C<=TCASE<=85C (rREFI/2)
tREFI2 REFab Fine Granularity, 85C<TCASE<=95C (rREFI/4)
tREFIsb REFsb Fine Granularity, 0C<=TCASE<=85C (rREFI/(2*n))
tREFIsb REFsb Fine Granularity, 85C<TCASE<=95C (rREFI/(4*n))
VDD must be within 66mV of VDDQ
DRAM Reference clock frequency tCK - Min (all grades)
DRAM Reference clock frequency tCK - Max (all grades)
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ)
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ)
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ)
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ)
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ)
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ)
Rj RMS value of N-UI Jitter, where N=4,5,6,...,30 (tCK_NUI_Rj_NoBUJ)
Dj pp value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Dj_NoBUJ)
Tj value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Tj_NoBUJ)
Tj definition for BER 1E-16
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio)
Input Clock Voltage Sensitivity (differential pp) (VRx_CK)
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK)
DQ Timing Width (tRx_DQ_tMargin)
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD)
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj)
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj)
Delay of any data lane relative to the DQS_t/DQS_c crossing (tRx_DQS2DQ)
Applied DCD to the DQS (tRx_DQS_DCD)
Applied Rj RMS to the DQS (tRx_DQS_Rj)
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj)
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS)
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ)
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1)
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1)
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1)
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye_Golden_Ref_Channel_1)
Injected Random wide band (10 MHz-1 GHz) Jitter (Rj_Stressed_Eye_Golden_Ref_Channel_1)
Injected voltage noise as PRBS23 or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1)
DFE tap range limit (\|Tap-2\| + \|Tap-3\| + \|Tap-4\|)
Minimum BER requirement (Rx Stressed Eye)
tCT_IS Connectivity Test - Min
tCT_IS Connectivity Test - Max
tCT_Enable Connectivity Test - Min
tCT_Enable Connectivity Test - Max
tCT_Valid Connectivity Test - Min
tCT_Valid Connectivity Test - Max
TEN AC Input High Voltage (VIH(AC)_TEN)
TEN DC Input High Voltage (VIH(DC)_TEN)
TEN DC Input Low Voltage (VIL(DC)_TEN)
TEN AC Input Low Voltage (VIL(AC)_TEN)
TEN Input signal Falling time (TF_input_TEN)
TEN Input signal Rising time (TR_input_TEN)
AC Input High Voltage (VIH(AC)_RESET)
DC Input High Voltage (VIH(DC)_RESET)
DC Input Low Voltage (VIL(DC)_RESET)
AC Input Low Voltage (VIL(AC)_RESET)
Rising time (TR_RESET)
RESET pulse width (tPW_RESET)
Mismatch between pull-up and pull-down MMPuPd, Min
Mismatch between pull-up and pull-down MMPuPd, Max
Mismatch DQ-DQ within byte variation pull-up MMPudd, Max
Mismatch DQ-DQ within byte variation pull-dn MMPddd, Max
Loopback LBDQS Output Low Time tLBQSL, Min (DDR5-3200)
Loopback LBDQS Output High Time tLBQSH, Min (DDR5-3200)
Loopback LBDQS to LBDQ Skew tLBDQSQ, Min (DDR5-3200)
Loopback LBDQ Output Time from LBDQS tLBQH, Min (DDR5-3200)
Loopback Data valid window tLBDVW, Min (DDR5-3200)
Single-ended VOH (output high measurement level for output SR)
Single-ended VOL (output low measurement level for output SR)
Loopback Single-ended VOH (output high measurement level for output SR)
Loopback Single-ended VOL (output low measurement level for output SR)
Single ended output slew rate SRQse, Min (DDR5-3200)
Single ended output slew rate SRQse, Max (DDR5-3200)
Differential VOHdiff (differential output high measurement level for output SR)
Differential VOLdiff (differential output low measurement level for output SR)
Differential output slew rate SRQdiff, Min (DDR5-3200)
Differential output slew rate SRQdiff, Max (DDR5-3200)
Tx DQS Rj RMS 1-UI jitter without BUJ tTx_DQS_1UI_Rj_NoBUJ, Max (DDR5-3200)
Tx DQS Dj pp 1-UI jitter without BUJ tTx_DQS_1UI_Dj_NoBUJ, Max (DDR5-3200)
Tx DQS Rj RMS N-UI jitter without BUJ tTx_DQS_NUI_Rj_NoBUJ, Max (DDR5-3200)
Tx DQS Dj pp N-UI jitter without BUJ tTx_DQS_NUI_Dj_NoBUJ, Max (DDR5-3200)
Tx DQ Rj RMS 1-UI jitter without BUJ tTx_DQ_1UI_Rj_NoBUJ, Max (DDR5-3200)
Tx DQ Dj pp 1-UI jitter without BUJ tTx_DQ_1UI_Dj_NoBUJ, Max (DDR5-3200)
Tx DQ Rj RMS N-UI jitter without BUJ tTx_DQ_NUI_Rj_NoBUJ, Max (DDR5-3200)
Tx DQ Dj pp N-UI jitter without BUJ tTx_DQ_NUI_Dj_NoBUJ, Max (DDR5-3200)
Tx DQS2DQ delay of any data lane relative to strobe lane, Min (DDR5-3200)
Tx DQS2DQ delay of any data lane relative to strobe lane, Max (DDR5-3200)
Tx DQ Stressed Eye Height SES 1UI TxEH_DQ_SES_1UI, Min (DDR5-3200)
Tx DQ Stressed Eye Width SES 1UI TxEW_DQ_SES_1UI, Min (DDR5-3200)
Tx DQ Stressed Eye Height SES 2UI TxEH_DQ_SES_2UI, Min (DDR5-3200)
Tx DQ Stressed Eye Width SES 2UI TxEW_DQ_SES_2UI, Min (DDR5-3200)
Tx DQ Stressed Eye Height SES 3UI TxEH_DQ_SES_3UI, Min (DDR5-3200)
Tx DQ Stressed Eye Width SES 3UI TxEW_DQ_SES_3UI, Min (DDR5-3200)
Tx DQ Stressed Eye Height SES 4UI TxEH_DQ_SES_4UI, Min (DDR5-3200)
Tx DQ Stressed Eye Width SES 4UI TxEW_DQ_SES_4UI, Min (DDR5-3200)
Tx DQ Stressed Eye Height SES 5UI TxEH_DQ_SES_5UI, Min (DDR5-3200)
Tx DQ Stressed Eye Width SES 5UI TxEW_DQ_SES_5UI, Min (DDR5-3200)
Module width (overall, Front)
Module width (between features, Front)
Contact group dimension (left, Front)
Contact group dimension (right, Front)
Edge dimension (Front, left)
Module height (Side)
Feature dimension (Back)
Module height with keep-out (Back)
Keep-out edge dimension (Back)
Bottom radius (Back)
Component label (Front, center)
Detail of Contacts A,F - dimension 0.60±0.03
Detail of Contacts E - dimension 1.50±0.05
Detail of Contacts E - dimension 0.2±0.15
Detail of Contacts E - dimension 0.20±0.15
Detail of Contacts E - dimension 5.95
Detail of Contacts E - dimension 3.85±0.1
Detail of Contacts E - dimension 4.30
Detail of Contacts E - dimension 3.35
Detail of Contacts D - keep-out note
Detail of Contacts D - Max 0.30
Detail of Contacts D - dimension 0.60±0.03
Keep-out note - Max 0.30
Keep-out note - Max 0.35
Keep-out note - Max 0.25
Detail A - dimension 14.60
Detail A - dimension 3.00
Detail B - dimension 8.00
Detail B - dimension 11.00
Detail F - SPD/TS component label
Module density
Register input loopback data
Register input loopback strobe
Register input alert
Register output A - command/address bus
Register output A - derror in
Register output B - command/address bus
Register output B - derror in
Front-side DRAM placements (row A path)
Back-side DRAM placements
DRAM byte mapping - row A
DRAM byte mapping - row B
Resistor value note (page2)
VDD - Voltage on VDD pin relative to Vss (Absolute Max)
VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Max)
VPP - Voltage on VPP pin relative to Vss (Absolute Max)
VIN, VOUT - Voltage on any pin relative to Vss (Absolute Max)
TSTG - Storage Temperature (Absolute Max)
tREFI1 REFab Normal (0°C <= TCASE <= 85°C)
tREFI1 REFab Normal (85°C < TCASE <= 95°C)
tREFI2 REFab Fine Granularity (0°C <= TCASE <= 85°C)
tREFI2 REFab Fine Granularity (85°C < TCASE <= 95°C)
tREFIsb REFsb Fine Granularity (0°C <= TCASE <= 85°C)
tREFIsb REFsb Fine Granularity (85°C < TCASE <= 95°C)
VDD Device Supply Voltage - Min (Low Freq Voltage Spec)
Rx Mask voltage - p-p (VciVW) Min
Rx Timing Window (TcIVW) Min
Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
Figure 5 caption
Clock driving topology
Figure 6
Random Jitter (Rj) definition
Deterministic Jitter (Dj) definition
Jitter violation warning
Table 2 abbreviations
Duty Cycle Error (tCK_Duty_UI_Error) Min
Duty Cycle Error (tCK_Duty_UI_Error) Min/Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) Min
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) Min
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) Min
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ) Min
Rj RMS value of N-UI Jitter, where N=2,3 (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ) Min
Dj pp value of N-UI Jitter, where N=2,3 (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ) Min
Tj value of N-UI Jitter, where N=2,3 (tCK_NUI_Tj_NoBUJ) Max
Rj RMS value of N-UI Jitter, where N=4,5,6,...,30 (tCK_NUI_Rj_NoBUJ) Min
Rj RMS value of N-UI Jitter, where N=4,5,6,...,30 (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Dj_NoBUJ) Min
Dj pp value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Tj_NoBUJ) Min
Tj value of N-UI Jitter, N=4,5,6,...,30 (tCK_NUI_Tj_NoBUJ) Max
Footnote 1
Footnote 2
Footnote 3
Footnote 4
Footnote 5
Footnote 6
Footnote 7
Footnote 8
Footnote 9
Footnote 10
Footnote 11
Footnote 12
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Min
Input Clock Voltage Sensitivity differential pp (VRx_CK) Min
Differential input high measurement level CK_t, CK_c (VIHdiffCK)
Differential input low measurement level CK_t, CK_c (VILdiffCK)
DQ Timing Width (tRx_DQ_tMargin) Max
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) Min
Degradation of timing width with DCD injection in DQS (dtRx_DQ_tMargin_DQS_DCD) Max
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) Min
Degradation of timing width with Rj injection in DQS (dtRx_DQ_tMargin_DQS_Rj) Max
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) Min
Degradation of timing width with both DCD and Rj injection in DQS (dtRx_DQ_tMargin_DQS_DCD_Rj) Max
Applied DCD to the DQS (tRx_DQS_DCD) Min
Applied Rj RMS to the DQS (tRx_DQS_Rj) Min
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Min
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) Min
Differential input high measurement level DQS_t, DQS_c (VIHdiffDQS)
Differential input low measurement level DQS_t, DQS_c (VILdiffDQS)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Min
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) Min
Golden Reference Channel 1 Characteristics as measured at TBD (Golden_Ref_Channel_1_Characteristics) Max
CT Mode tCT_IS Min
CT Mode tCT_IS Max
CT Mode tCT_Enable Min
CT Mode tCT_Enable Max
CT Mode tCT_Valid Min
CT Mode tCT_Valid Max
TEN Input signal Falling time (TF_input_TEN) Min
TEN Input signal Rising time (TR_input_TEN) Min
RESET_n Rising time (TR_RESET) Min
RESET pulse width (tPW_RESET) Max
RZQ assumption
RON34Pd Min
RON34Pd Nom
RON34Pd Max
RON34Pu Min
RON34Pu Nom
RON34Pu Max
RON48Pd Min
RON48Pd Nom
RON48Pd Max
RON48Pu Min
RON48Pu Nom
RON48Pu Max
Loopback RON34Pd Min
Loopback RON34Pd Nom
Loopback RON34Pd Max
Loopback RON34Pu Min
Loopback RON34Pu Nom
Loopback RON34Pu Max
Loopback MMPuPd Min
Loopback MMPuPd Max
Loopback MMPudd Max
Loopback MMPddd Max
Alert RONPd Min
Alert RONPd Max
CT RONPd_CT Max
CT RONPu_CT Max
VOH Loopback Output high measurement level (for output SR)
VOL Loopback Output low measurement level (for output SR)
Front - module width (overall)
Front - module width
Front - left edge to contact group dimension
Front - contact group dimension
Front - left contact dimension
Front - right contact dimension
Center component callout
Back - module height (overall)
Back - keep-out/edge dimension
Back - component callout SPD/TS
Side - module thickness
Side - max dimension
Detail of Contacts A, F - height
Detail of Contacts A, F - width with tolerance
Detail of Contacts D - height
Detail of Contacts D - width with tolerance
Detail of Contacts B/D - keep-out note
Pin reference numbers
Document title
Latest revision history entry
Product description
block_diagram_title
module_organization
register_component
register_input_signals_DCA
register_input_signals_DCS
register_input_signals_DPAR
register_input_clock
register_input_DRST
register_input_QLBD_QLBS_ALERT
register_output_A_side_QACA
register_output_A_side_QACS0
register_output_A_side_QACK
register_output_A_side_QRST
register_output_A_side_DERROR_IN
register_output_A_side_DLBD
register_output_A_side_DLBS
register_output_B_side_QACA
register_output_B_side_QACS0
register_output_B_side_QACK
register_output_B_side_QRST
register_output_B_side_DERROR_IN
register_output_B_side_DLBD
register_output_B_side_DLBS
dram_placements_front_row
dram_placements_back_row
resistor_value_note
dram_group_A_placements
dram_group_A_signals
dram_group_B_placements
dram_group_B_signals
dram_zq_resistor_note
Absolute Maximum DC Rating - Voltage on VDD pin relative to Vss (VDD)
Absolute Maximum DC Rating - Voltage on VDDQ pin relative to Vss (VDDQ)
Absolute Maximum DC Rating - Voltage on VPP pin relative to Vss (VPP)
Absolute Maximum DC Rating - Voltage on any pin relative to Vss (VIN, VOUT)
Absolute Maximum DC Rating - Storage Temperature (TSTG)
tREFI parameter - REFab Normal tREFI1 [0°C <= TCASE <= 85°C]
tREFI parameter - REFab Normal tREFI1 [85°C < TCASE <= 95°C]
tREFI parameter - REFab Fine Granularity tREFI2 [0°C <= TCASE <= 85°C]
tREFI parameter - REFab Fine Granularity tREFI2 [85°C < TCASE <= 95°C]
tREFI parameter - REFsb Fine Granularity tREFIsb [0°C <= TCASE <= 85°C]
tREFI parameter - REFsb Fine Granularity tREFIsb [85°C < TCASE <= 95°C]
Recommended DC Operating Condition - Device Supply Voltage (VDD) Min
Recommended DC Operating Condition - Device Supply Voltage (VDD) Typ
Recommended DC Operating Condition - Device Supply Voltage (VDD) Max
Recommended DC Operating Condition - Device Supply Voltage (VDD) Z(f) Zmax 2MHz-10MHz
Recommended DC Operating Condition - Device Supply Voltage (VDD) Z(f) Zmax 20MHz
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Min
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Typ
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Max
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Z(f) Zmax 2MHz-10MHz
Recommended DC Operating Condition - Supply Voltage for I/O (VDDQ) Z(f) Zmax 20MHz
Recommended DC Operating Condition - Core Power Voltage (VPP) Min
Recommended DC Operating Condition - Core Power Voltage (VPP) Typ
Recommended DC Operating Condition - Core Power Voltage (VPP) Max
Recommended DC Operating Condition - Core Power Voltage (VPP) Z(f) Zmax 2MHz-10MHz
Recommended DC Operating Condition - Core Power Voltage (VPP) Z(f) Zmax 20MHz
tAAmin (ns) [(top row)]
tRCDmin/tRPmin (ns) [(top row)]
Read CL Write CWL [(top row)]
tCK(AVG) min [(top row)]
tCK(AVG) max [(top row)]
NOTE [(top row)]
tAAmin (ns) [3200C]
tRCDmin/tRPmin (ns) [3200C]
Read CL Write CWL [3200C]
tCK(AVG) min [3200C]
tCK(AVG) max [3200C]
tAAmin (ns) [3200BN/3200B]
tRCDmin/tRPmin (ns) [3200BN/3200B]
Read CL Write CWL [3200BN/3200B]
tCK(AVG) min [3200BN/3200B]
tCK(AVG) max [3200BN/3200B]
tAAmin (ns) [3200AN]
tRCDmin/tRPmin (ns) [3200AN]
Read CL Write CWL [3200AN]
tCK(AVG) [3200AN]
tAAmin (ns) [3600C]
tRCDmin/tRPmin (ns) [3600C]
Read CL Write CWL [3600C]
tCK(AVG) min [3600C]
tCK(AVG) max [3600C]
tAAmin (ns) [3600BN/3600B]
tRCDmin/tRPmin (ns) [3600BN/3600B]
Read CL Write CWL [3600BN/3600B]
tCK(AVG) min [3600BN/3600B]
tCK(AVG) max [3600BN/3600B]
tAAmin (ns) [3600AN]
tRCDmin/tRPmin (ns) [3600AN]
Read CL Write CWL [3600AN]
tCK(AVG) [3600AN]
tAAmin (ns) [4000C]
tRCDmin/tRPmin (ns) [4000C]
Read CL Write CWL [4000C]
tCK(AVG) min [4000C]
tCK(AVG) max [4000C]
tAAmin (ns) [4000BN/4000B]
tRCDmin/tRPmin (ns) [4000BN/4000B]
Read CL Write CWL [4000BN/4000B]
tCK(AVG) min [4000BN/4000B]
tCK(AVG) max [4000BN/4000B]
tAAmin (ns) [4000AN]
tRCDmin/tRPmin (ns) [4000AN]
Read CL Write CWL [4000AN]
tCK(AVG) [4000AN]
tAAmin (ns) [4400C]
tRCDmin/tRPmin (ns) [4400C]
Read CL Write CWL [4400C]
tCK(AVG) min [4400C]
tCK(AVG) max [4400C]
tAAmin (ns) [4400BN/4400B]
tRCDmin/tRPmin (ns) [4400BN/4400B]
Read CL Write CWL [4400BN/4400B]
tCK(AVG) min [4400BN/4400B]
tCK(AVG) max [4400BN/4400B]
tAAmin (ns) [4400AN]
tRCDmin/tRPmin (ns) [4400AN]
Read CL Write CWL [4400AN]
tCK(AVG) [4400AN]
tAAmin (ns) [4800C]
tRCDmin/tRPmin (ns) [4800C]
Read CL Write CWL [4800C]
tCK(AVG) min [4800C]
tCK(AVG) max [4800C]
tAAmin (ns) [4800BN]
tRCDmin/tRPmin (ns) [4800BN]
Read CL Write CWL [4800BN]
tCK(AVG) min [4800BN]
tCK(AVG) max [4800BN]
tAAmin (ns) [4800B]
tRCDmin/tRPmin (ns) [4800B]
Read CL Write CWL [4800B]
tCK(AVG) min [4800B]
tCK(AVG) max [4800B]
tAAmin (ns) [4800AN]
tRCDmin/tRPmin (ns) [4800AN]
Read CL Write CWL [4800AN]
tCK(AVG) [4800AN]
Spec table title
Module width (inner)
Front contact height
Module height (Back overall)
Back left feature width
Back feature width
Side pin pitch
Notch / key dimension
Detail of Contacts A,F - height
Detail of Contacts A,F - width
Detail of Contacts E - dimension 1
Detail of Contacts E - dimension 2
Detail of Contacts E - dimension 3
Detail of Contacts E - dimension 4
Detail of Contacts E - dimension 5
Detail of Contacts E - dimension 6
Detail of Contacts B - dimension 1
Detail of Contacts B - dimension 2
Detail of Contacts B - dimension 3
Detail of Contacts B - dimension 4
Detail of Contacts B - Pin 35
Detail of Contacts B - Pin 47
Detail of Contacts C - dimension 1
Detail of Contacts C - dimension 2
Detail of Contacts C - dimension 3
Detail of Contacts C - dimension 4
Detail of Contacts C - Pin 105
Detail of Contacts C - Pin 117
Detail of Contacts (keep-out) - dimension
Non-matarized keep out area note
Keep out area - Max 0.30
Keep out area - Max 0.35
Keep out area - Max 0.25
Detail of Contacts D - width
Keep out area D - Max 0.30 (a)
Keep out area D - Max 0.35
Keep out area D - Max 0.30 (b)
Detail E - dimension 1
Detail E - dimension 2
Detail A callout
Detail B callout
Detail C callout
Detail D callout
Detail E callout
Detail F callout
Registering / Clock Driver callout
SPD callout
TS callout 1
TS callout 2
Back detail dimension 8.00
Back detail dimension 11.00
Module IDD basis
module_configuration
module_length_overall
module_length_inner
edge_to_first_feature
key_notch_offset
contact_span
dim_2.10
dim_2.70
key_notch_position
card_thickness
card_thickness_qualifier
fillet_radius
dim_14.60
back_dim_17.60
back_dim_30.75
registering_clock_driver_label
spd_label
ts_label
detail_a_dim_3.35
detail_a_dim_8.00
detail_a_dim_11.00
detail_contacts_af_dim_0.85
detail_contacts_af_dim_0.60
detail_contacts_af_dim_1.50
detail_contacts_af_dim_0.2
detail_contacts_af_dim_0.20
detail_e_dim_5.95
detail_e_dim_3.85
detail_e_dim_4.30
detail_e_dim_2.10
detail_e_dim_3.35
detail_b_dim_2.10
detail_b_dim_2.60
detail_b_dim_9.35
detail_b_dim_10.20
detail_b_pins
detail_c_dim_2.10
detail_c_dim_2.60
detail_c_dim_9.35
detail_c_dim_10.20
detail_c_pins
detail_d_dim_0.85
detail_d_dim_0.60
detail_d_dim_2.60
detail_d_dim_2.10
keep_out_max_0.30
keep_out_max_0.35
keep_out_max_0.25
keep_out_max_0.30_d
pin_callouts
detail_markers
tolerance_note
units_note