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HMAT14JWRRB120N (SK hynix)
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| Memory Class | rdimm |
|---|---|
| Pin Count | 288 |
| Capacity Gb | 256 |
| Voltage Vdd V | 1.2 |
| Ecc | Supports ECC error correction and detection |
| Speed Mt S | 2933 |
| Die Density Gb | 16 |
| Registered | true |
| Memory Generation | ddr4 |
| Product Name | DDR4 SDRAM Registered DIMM Based on 16Gb J-die |
| Act To Pre Command Period Tras Max | |
| Act To Pre Command Period Tras Min | |
| Bank Address In A Bg | |
| Bg Address | |
| Ca Parity | |
| Cas Latency | |
| Cl Nrcd Nrp |
| Cl Trcd Trp |
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| Column Address |
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| Component Composition |
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| Corner Radius |
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| Data Transfer Rates |
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| Die Type |
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| Document Revision |
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| Grade |
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| Idd0 |
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| Idd0a |
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| Idd1 |
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| Idd1a |
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| Idd2n |
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| Idd2na |
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| Idd2nd |
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| Idd2ng |
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| Idd2nl |
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| Idd2np |
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| Idd2nt |
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| Idd2p |
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| Idd2q |
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| Idd3n |
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| Idd3na |
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| Idd3p |
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| Idd4r |
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| Idd4ra |
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| Idd4w |
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| Idd4wa |
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| Idd4wc |
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| Idd4wp |
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| Idd5f2 |
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| Idd5f4 |
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| Idd6a |
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| Idd6e |
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| Idd6n |
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| Idd6r |
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| Idd7 |
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| Idd8 |
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| Internal Banks |
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| Ipp0 |
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| Ipp1 |
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| Ipp2n |
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| Ipp2p |
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| Ipp3n |
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| Ipp3p |
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| Ipp4r |
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| Ipp4w |
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| Ipp5f2 |
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| Ipp5f4 |
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| Ipp6a |
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| Ipp6e |
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| Ipp6n |
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| Ipp6r |
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| Ipp7 |
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| Ipp8 |
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| Of Bank Groups |
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| Of Ranks |
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| Pin Number Callout |
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| Pre Fetch |
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| Row Address |
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| Tck |
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| Temperature Sensor |
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| Tras |
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| Trc |
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| Trcd |
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| Trp |
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| Units |
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| Vddq |
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| Vddspd |
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| Voltage Vpp V |
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| Write Crc |
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| SKU | HMAT14JWRRB120N |
|---|
| Based on die | |
|---|---|
| Revision | |
| Date | |
| Disclaimer | |
| Intended use | |
| Power Supply VDD | |
| Standard compliance | |
| Bank Grouping | |
| Data Strobe | |
| Burst Length | |
| On-Die Termination | |
| RoHS compliance | |
| Per DRAM Addressability | |
| Internal Vref DQ | |
| Organization | |
| Speed grade (MT/s) | |
| Downbinning support | |
| Rank Address | |
| Chip ID | |
| Page size | |
| Absolute Maximum DC Rating - VDD (Voltage on VDD pin relative to Vss) | |
| Absolute Maximum DC Rating - VDDQ (Voltage on VDDQ pin relative to Vss) | |
| Absolute Maximum DC Rating - VPP (Voltage on VPP pin relative to Vss) | |
| Absolute Maximum DC Rating - VIN, VOUT (Voltage on any pin except VREFCA relative to Vss) | |
| Absolute Maximum DC Rating - TSTG (Storage Temperature) | |
| DRAM Component Operating Temperature Range - TOPER Normal Operating Temperature Range | |
| DRAM Component Operating Temperature Range - Extended Temperature Range | |
| Recommended DC Operating Conditions - VDD (Supply Voltage) | |
| Recommended DC Operating Conditions - VDDQ (Supply Voltage for Output) | |
| Recommended DC Operating Conditions - VPP (Supply Voltage for DRAM Activating) | |
| DDR4-2400 Speed Bin | |
| DDR4-2400 CL-nRCD-nRP | |
| DDR4-2400 tAA (Internal read command to first data) | |
| DDR4-2400 tRCD (ACT to internal read or write delay time) | |
| DDR4-2400 tRP (PRE command period) | |
| DDR4-2400 tRAS (ACT to PRE command period) | |
| DDR4-2400 tRC (ACT to ACT or REF command period) | |
| DDR4-2400 CWL=9,11 CL=13 tCK(AVG) | |
| DDR4-2400 CWL=9,11 CL=14 tCK(AVG) | |
| DDR4-2400 CWL=10,12 CL=14 tCK(AVG) | |
| DDR4-2400 CWL=10,12 CL=15 tCK(AVG) | |
| DDR4-2400 CWL=10,12 CL=16 tCK(AVG) | |
| DDR4-2400 CWL=11,14 CL=16 tCK(AVG) | |
| DDR4-2400 CWL=11,14 CL=18 tCK(AVG) | |
| DDR4-2400 CWL=11,14 CL=20 tCK(AVG) | |
| DDR4-2400 CWL=12,16 CL=18 tCK(AVG) | |
| DDR4-2400 CWL=12,16 CL=20 tCK(AVG) | |
| DDR4-2400 CWL=12,16 CL=22 tCK(AVG) | |
| DDR4-2400 Supported CL Settings | |
| DDR4-2400 Supported nRCD Timings minimum | |
| DDR4-2400 Supported nRP Timings minimum | |
| DDR4-2400 Supported CWL Settings | |
| DDR4-2666 Speed Bin | |
| DDR4-2666 CL-nRCD-nRP | |
| DDR4-2666 tAA | |
| DDR4-2666 tRCD | |
| DDR4-2666 tRP | |
| DDR4-2666 tRAS | |
| DDR4-2666 tRC | |
| DDR4-2666 CWL=9,11 CL=14 tCK(AVG) | |
| DDR4-2666 CWL=10,12 CL=16 tCK(AVG) | |
| DDR4-2666 CWL=11,14 CL=18 tCK(AVG) | |
| DDR4-2666 CWL=11,14 CL=20 tCK(AVG) | |
| DDR4-2666 CWL=12,16 CL=20 tCK(AVG) | |
| DDR4-2666 CWL=12,16 CL=22 tCK(AVG) | |
| DDR4-2666 CWL=14,18 CL=22 tCK(AVG) | |
| DDR4-2666 CWL=14,18 CL=24 tCK(AVG) | |
| DDR4-2666 Supported CL Settings | |
| DDR4-2666 Supported nRCD Timings minimum | |
| DDR4-2666 Supported nRP Timings minimum | |
| DDR4-2666 Supported CWL Settings | |
| DDR4-2933 Speed Bin | |
| DDR4-2933 CL-nRCD-nRP | |
| DDR4-2933 tAA | |
| DDR4-2933 tRCD | |
| DDR4-2933 tRP | |
| DDR4-2933 tRAS | |
| DDR4-2933 tRC | |
| DDR4-2933 CWL=9,11 CL=14 tCK(AVG) | |
| DDR4-2933 CWL=10,12 CL=16 tCK(AVG) | |
| DDR4-2933 CWL=11,14 CL=18 tCK(AVG) | |
| DDR4-2933 CWL=11,14 CL=20 tCK(AVG) | |
| DDR4-2933 CWL=12,16 CL=20 tCK(AVG) | |
| DDR4-2933 CWL=12,16 CL=22 tCK(AVG) | |
| DDR4-2933 CWL=14,18 CL=22 tCK(AVG) | |
| DDR4-2933 CWL=14,18 CL=24 tCK(AVG) | |
| DDR4-2933 CWL=16,20 CL=24 tCK(AVG) | |
| DDR4-2933 CWL=16,20 CL=25 tCK(AVG) | |
| DDR4-2933 Supported CL Settings | |
| DDR4-2933 Supported nRCD Timings minimum | |
| DDR4-2933 Supported nRP Timings minimum | |
| DDR4-2933 Supported CWL Settings | |
| DDR4-3200 Speed Bin | |
| DDR4-3200 CL-nRCD-nRP | |
| DDR4-3200 tAA | |
| DDR4-3200 tRCD | |
| DDR4-3200 tRP | |
| DDR4-3200 tRAS | |
| DDR4-3200 tRC | |
| DDR4-3200 CWL=9,11 CL=14 tCK(AVG) | |
| DDR4-3200 CWL=10,12 CL=16 tCK(AVG) | |
| DDR4-3200 CWL=11,14 CL=18 tCK(AVG) | |
| DDR4-3200 CWL=11,14 CL=20 tCK(AVG) | |
| DDR4-3200 CWL=12,16 CL=20 tCK(AVG) | |
| DDR4-3200 CWL=12,16 CL=22 tCK(AVG) | |
| DDR4-3200 CWL=14,18 CL=22 tCK(AVG) | |
| DDR4-3200 CWL=14,18 CL=24 tCK(AVG) | |
| DDR4-3200 CWL=16,20 CL=22 tCK(AVG) | |
| DDR4-3200 CWL=16,20 CL=24 tCK(AVG) | |
| DDR4-3200 CWL=16,20 CL=25 tCK(AVG) | |
| DDR4-3200 Supported CL Settings | |
| DDR4-3200 Supported nRCD Timings minimum | |
| DDR4-3200 Supported nRP Timings minimum | |
| DDR4-3200 Supported CWL Settings | |
| DLL state for speed bin table | |
| Gear Down Mode requirement for speed bins | |
| Max simultaneous Refresh commands per logical rank (8Gb and below die) | |
| Max postponed-row refresh interval (8Gb and below die) | |
| Max pulled-in Refresh commands per logical rank (8Gb and below die) | |
| Max REF commands per logical rank within 2 x tREFI_slr | |
| Max burst Refresh commands per 3D Stacked DDR4 package (16Gb and above die) | |
| Max 16 Refresh commands issue window - FGR1 mode | |
| Max 16 Refresh commands issue window - FGR2 mode | |
| Max 16 Refresh commands issue window - FGR4 mode | |
| Max postponed-row refresh interval - 2H 3D Stacked | |
| Max postponed-row refresh interval - 4H 3D Stacked | |
| Max pulled-in Refresh commands per 3D Stacked DDR4 package (16Gb and above die) | |
| Max postponed Refresh commands per package for Self-Refresh entry (16Gb and above die) | |
| tREF_stagger (minimum stagger between refresh commands to different logical ranks) | |
| tRFC_slr1 (1x mode) - 16Gb Default | |
| tRFC_slr1 (1x mode) - 16Gb Optional | |
| tRFC_slr2 (2x mode) - 16Gb Default | |
| tRFC_slr2 (2x mode) - 16Gb Optional | |
| tRFC_slr4 (4x mode) - 16Gb Default | |
| tRFC_slr4 (4x mode) - 16Gb Optional | |
| tRFC_dlr1 (1x mode) - 16Gb Default | |
| tRFC_dlr1 (1x mode) - 16Gb Optional | |
| tRFC_dlr2 (2x mode) - 16Gb Default | |
| tRFC_dlr2 (2x mode) - 16Gb Optional | |
| tRFC_dlr4 (4x mode) - 16Gb Default | |
| tRFC_dlr4 (4x mode) - 16Gb Optional | |
| tREFI_slr1 (1x mode) - 0 oC =< TCASE =< 85 oC | |
| tREFI_slr1 (1x mode) - 85 oC < TCASE =< 95 oC | |
| tREFI_slr2 (2x mode) - 0 oC =< TCASE =< 85 oC | |
| tREFI_slr2 (2x mode) - 85 oC < TCASE =< 95 oC | |
| tREFI_slr4 (4x mode) - 0 oC =< TCASE =< 85 oC | |
| tREFI_slr4 (4x mode) - 85 oC < TCASE =< 95 oC | |
| IDD calculation basis | |
| IDD5B1 | |
| IPP5B1 | |
| Module length (overall, Front) | |
| Module length (PCB, Front) | |
| Module height (Front) | |
| PCB height to notch (Front) | |
| Contact field length (left, Front) | |
| Contact field length (right, Front) | |
| Top edge offset (Front) | |
| Detail E dimension (Front) | |
| Edge thickness (Front) | |
| Component zone width (Front) | |
| Notch position (Back) | |
| Corner radius (Back) | |
| Notch dimension (Back) | |
| Registering Clock Driver location | |
| SPD/TS location | |
| Component dimension callout | |
| Contact thickness (Detail of Contacts A, F) | |
| Contact dimension (Detail of Contacts A, F) | |
| Contact width (Detail of Contacts A, F) | |
| Contact dimension (Detail of Contacts E) | |
| Contact dimension (Detail of Contacts B) | |
| Pin reference (Detail of Contacts B) | |
| Contact dimension (Detail of Contacts C) | |
| Pin reference (Detail of Contacts C) | |
| Contact thickness (Detail of Contacts D) | |
| Contact dimension (Detail of Contacts D) | |
| Keep-out area (Detail of Contacts D) | |
| Keep-out dimension (Detail of Contacts D) | |
| Keep-out area (second callout) | |
| Detail F dimension | |
| Dimensional tolerance (general) | |
| Drawing note | |
| product_title | |
| manufacturer | |
| document_date | |
| disclaimer | |
| Compliance | |
| On-Die Termination (ODT) | |
| RoHS | |
| Downbinning note | |
| Bank Address - # of Bank Groups | |
| Bank Address - BG Address | |
| Bank Address - Bank Address in a BG | |
| Internal read command to first data (tAA) min | |
| Internal read command to first data (tAA) max | |
| ACT to internal read or write delay time (tRCD) min | |
| ACT to internal read or write delay time (tRCD) max | |
| PRE command period (tRP) min | |
| PRE command period (tRP) max | |
| ACT to ACT or REF command period (tRC) min | |
| ACT to ACT or REF command period (tRC) max | |
| CWL=9,11 CL=13 tCK(AVG) | |
| CWL=9,11 CL=14 tCK(AVG) min | |
| CWL=9,11 CL=14 tCK(AVG) max | |
| CWL=10,12 CL=14 tCK(AVG) | |
| CWL=10,12 CL=15 tCK(AVG) | |
| CWL=10,12 CL=16 tCK(AVG) min | |
| CWL=10,12 CL=16 tCK(AVG) max | |
| CWL=11,14 CL=16 tCK(AVG) | |
| CWL=11,14 CL=18 tCK(AVG) min | |
| CWL=11,14 CL=18 tCK(AVG) max | |
| CWL=11,14 CL=20 tCK(AVG) min | |
| CWL=11,14 CL=20 tCK(AVG) max | |
| CWL=12,16 CL=18 tCK(AVG) | |
| CWL=12,16 CL=20 tCK(AVG) min | |
| CWL=12,16 CL=20 tCK(AVG) max | |
| CWL=12,16 CL=22 tCK(AVG) min | |
| CWL=12,16 CL=22 tCK(AVG) max | |
| CWL=14,18 CL=20 tCK(AVG) | |
| CWL=14,18 CL=22 tCK(AVG) min | |
| CWL=14,18 CL=22 tCK(AVG) max | |
| CWL=14,18 CL=24 tCK(AVG) min | |
| CWL=14,18 CL=24 tCK(AVG) max | |
| CWL=16,20 CL=22 tCK(AVG) | |
| CWL=16,20 CL=23 tCK(AVG) | |
| CWL=16,20 CL=24 tCK(AVG) min | |
| CWL=16,20 CL=24 tCK(AVG) max | |
| CWL=16,20 CL=25 tCK(AVG) min | |
| CWL=16,20 CL=25 tCK(AVG) max | |
| Supported CL Settings | |
| Supported nRCD Timings minimum | |
| Supported nRP Timings minimum | |
| Supported CWL Settings | |
| tREFI_slr1 (1x mode), 0 oC =< TCASE =< 85 oC | |
| tREFI_slr1 (1x mode), 85 oC < TCASE =< 95 oC | |
| tREFI_slr2 (2x mode), 0 oC =< TCASE =< 85 oC | |
| tREFI_slr2 (2x mode), 85 oC < TCASE =< 95 oC | |
| tREFI_slr4 (4x mode), 0 oC =< TCASE =< 85 oC | |
| tREFI_slr4 (4x mode), 85 oC < TCASE =< 95 oC | |
| Module length (overall) | |
| Module length (between notches / PCB) | |
| Module height (front, PCB to top of components region) | |
| Module height (side view) | |
| PCB height (front) | |
| Contact field length (front, left) | |
| Contact field length (front, right) | |
| Top edge dimension | |
| Top edge dimension (2.10) | |
| Notch / key dimension | |
| Default dimensional tolerance | |
| Contact area width (14.10) | |
| Contact area dimension (3.00) | |
| Pin reference dimension (8.00) | |
| Pin reference dimension (11.00) | |
| Contact pad dimension (0.85) | |
| Contact pad dimension (0.60) | |
| Contact detail dimension (1.50) | |
| Contact detail dimension (0.2) | |
| Contact detail dimension (0.20) | |
| Detail of Contacts E dimension (5.95) | |
| Detail of Contacts E dimension (3.85) | |
| Detail of Contacts E dimension (4.30) | |
| Contact tab range (1.95~2.20) | |
| Contact tab range (2.45~2.70) | |
| Detail of Contacts B/C dimension (9.35) | |
| Detail of Contacts B/C dimension (10.20) | |
| Detail of Contacts D dimension (0.85) | |
| Detail of Contacts D dimension (0.60) | |
| Non-metalized keep out area (Max 0.25) | |
| Non-metalized keep out area (Max 0.35) | |
| Non-metalized keep out area (Max 0.21) | |
| Detail F dimension (31.25) | |
| Detail F dimension (1.40mm) | |
| Detail F dimension (4.1mm max) | |
| Dimensional units | |
| Drawing title | |
| Module designation |
