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INTEL GAUDI 3 AI ACCELERATOR (Intel Gaudi)
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| Memory Bandwidth Tb S | 3.7 |
|---|---|
| Process Node | TSMC 5nm process |
| Host Interface | PCIe Gen5 X16 |
| Tdp W | 900 |
| Memory Type | HBM2E |
| Gpu Memory Gb | 128 |
| Fp8 Tflops Dense | 1800 |
| Fp32 Tflops | 229 |
| Fp16 Bf16 Tflops Dense | 1678 |
| Product Name | |
| Tf32 Tflops Dense |
| SKU | INTEL GAUDI 3 AI ACCELERATOR |
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| Document title | |
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| Document version/date | |
| Architecture generation | |
| Compute dies |
| MME engines |
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| TPC engines |
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| RDMA NIC ports |
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| HBM chips |
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| Unified HBM capacity |
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| FP8 and BF16 compute |
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| HBM2e memory capacity |
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| BF16 MME TFLOPS |
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| FP8 MME TFLOPS |
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| BF16 Vector TFLOPS |
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| MME Units |
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| TPC Units |
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| On-die SRAM Capacity |
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| On-die SRAM Bandwidth (read/write) |
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| Networking (bidirectional) |
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| Host Interface Peak BW |
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| Media Decoders |
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| Key functions: Compute Engines - MMEs |
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| Key functions: Compute Engines - TPCs |
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| Media Engines - Media Decoder Engines (DECs) |
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| Media Engines - Rotator Engines (ROT) |
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| Memory - L2 Cache |
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| Memory - HBM2e |
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| Networking - Host port |
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| Networking - Network ports |
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| Physical partitioning - DCOREs |
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| Per-DCORE MMEs |
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| Per-DCORE TPCs |
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| Per-DCORE L2 Cache |
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| PCIe total bandwidth |
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| Peak TFLOP/Sec - MME (Matrix) FP8 |
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| Peak TFLOP/Sec - MME (Matrix) BF16 |
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| Peak TFLOP/Sec - MME (Matrix) FP16 (signed) |
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| Peak TFLOP/Sec - MME (Matrix) TF32 |
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| Peak TFLOP/Sec - MME (Matrix) FP32 |
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| Peak TFLOP/Sec - TPC (Vector) FP8 |
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| Peak TFLOP/Sec - TPC (Vector) BF16 |
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| Peak TFLOP/Sec - TPC (Vector) FP16 |
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| Peak TFLOP/Sec - TPC (Vector) FP32 |
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| MME count |
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| MME parallel operations |
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| MACs per MME |
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| Peak throughput per MME chip |
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| MACs per cycle per MME |
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| MME large unit input data per cycle |
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| MME array organization |
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| L2 cache (pipelining context) |
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| MME supported datatypes |
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| MME accumulator |
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| TPC generation |
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| TPC width |
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| TPC supported floating datatypes |
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| TPC supported integer datatypes |
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| Media decoding units |
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| Video format - HEVC |
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| Video format - H.264/SVC/MVC |
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| Video format - VP9 |
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| Image format - JPEG |
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| Image format - Progressive JPEG |
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| Post processing - max down-scale output |
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| Post processing - up-scaling |
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| Post processing channels per decoder block |
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| Decoder performance - HEVC |
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| Decoder performance - VP9 |
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| Decoder performance - H.264 |
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| Decoder performance - Jpeg 420 |
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| Decoder input stream format |
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| Decoder output stream format |
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| Rotator engine transformations |
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| On-die SRAM size |
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| On-die SRAM L2 split |
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| HBM2e frequency |
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| HBM peak bandwidth |
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| HBM2e device capacity |
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| HBM total capacity |
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| PCIe |
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| PCIe Peak BW |
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| On-die-SRAM |
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| On-die-SRAM BW |
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| Cache L2 throughput |
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| Cache L3 throughput |
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| Cache capacity & set-associativity |
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| HBM instances |
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| HBM total capacity (memory subsystem) |
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| HBM total bandwidth (memory subsystem) |
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| NIC ports |
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| Aggregation Engines |
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| NIC aggregated bandwidth per direction |
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| NIC RDMA protocol |
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| Collective offload min buffer size |
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| Congestion control schemes |
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| In-network reduction operations |
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| In-network reduction datatypes |
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| Example cluster scale |
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| Sub-cluster leaf switches |
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| Cluster spine switches |
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| Product line - generations |
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| Copyright/legal code |
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