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SK hynix HMCT04MEERAXXXN: rdimm, 128, 4400 | rackspecs

Server Memory

SK hynix HMCT04MEERAXXXN

HMCT04MEERAXXXN (SK hynix)

Memory Class

rdimm

Capacity Gb

128

Speed Mt S

4400

Memory Generation

ddr5

Specifications

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Other

Speed Mt S	4400
Memory Class	rdimm
Die Density Gb	16
Registered	true
Capacity Gb	128
Voltage Vdd V	1.1
Height Mm	31.25±0.15
Memory Generation	ddr5
Rank Organization	128GB (4Rx4)
Ecc	On-Die ECC; ECC Transparency and Error Scrub
Product Name	DDR5 SDRAM 3DS R-DIMM Based on 16Gb M-die
Bank Address In A Bg
Bg Address
Cl Nrcd Nrp
Cl Trcd Trp
Column Address
Component Composition
Corner Radius

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Vendor-specific

Module family header
Document date
Specification disclaimer
Organization
tAA
Page size
VDD - Voltage on VDD pin relative to Vss (Absolute Maximum DC Rating)
VDDQ - Voltage on VDDQ pin relative to Vss (Absolute Maximum DC Rating)
VPP - Voltage on VPP pin relative to Vss (Absolute Maximum DC Rating)
VIN, VOUT - Voltage on any pin relative to Vss (Absolute Maximum DC Rating)
TSTG - Storage Temperature (Absolute Maximum DC Rating)
VDD - Device Supply Voltage (Recommended DC Operating Conditions) Min.
VDD - Device Supply Voltage (Recommended DC Operating Conditions) Typ.
VDD - Device Supply Voltage (Recommended DC Operating Conditions) Max.
VDD - Zmax Z(f) Spec (Freq: 2Mhz to 10Mhz)
VDD - Zmax Z(f) Spec (Freq: 20Mhz)
VDDQ - Supply Voltage for I/O (Recommended DC Operating Conditions) Min.
VDDQ - Supply Voltage for I/O (Recommended DC Operating Conditions) Typ.
VDDQ - Supply Voltage for I/O (Recommended DC Operating Conditions) Max.
VDDQ - Zmax Z(f) Spec (Freq: 2Mhz to 10Mhz)
VDDQ - Zmax Z(f) Spec (Freq: 20Mhz)
VPP - Core Power Voltage (Recommended DC Operating Conditions) Min.
VPP - Core Power Voltage (Recommended DC Operating Conditions) Typ.
VPP - Core Power Voltage (Recommended DC Operating Conditions) Max.
VPP - Zmax Z(f) Spec (Freq: 2Mhz to 10Mhz)
VPP - Zmax Z(f) Spec (Freq: 20Mhz)
Read command to first data (tAA min)
Read command to first data (tAA max)
Activate to Read or Write command delay time (tRCD min)
Activate to Read or Write command delay time (tRCD max)
Row Precharge Time (tRP min)
Row Precharge Time (tRP max)
Activate to Precharge command period (tRAS min)
Activate to Precharge command period (tRAS max)
Activate to Activate or Refresh command period (tRC min)
Activate to Activate or Refresh command period (tRC max)
CAS Write Latency (CWL)
Down Bin -: tAAmin
Down Bin -: tRCDmin tRP-min
Down Bin -: Read CL
Down Bin -: tCK(AVG) min
Down Bin -: tCK(AVG) max
Down Bin 3200C: tAAmin
Down Bin 3200C: tRCDmin tRP-min
Down Bin 3200C: Read CL
Down Bin 3200C: tCK(AVG) min
Down Bin 3200C: tCK(AVG) max
Down Bin 3200BN,B: tAAmin
Down Bin 3200BN,B: tRCDmin tRP-min
Down Bin 3200BN,B: Read CL
Down Bin 3200BN,B: tCK(AVG) min
Down Bin 3200BN,B: tCK(AVG) max
Down Bin 3200AN: tAAmin
Down Bin 3200AN: tRCDmin tRP-min
Down Bin 3200AN: Read CL
Down Bin 3200AN: tCK(AVG)
Down Bin 3600C: tAAmin
Down Bin 3600C: tRCDmin tRP-min
Down Bin 3600C: Read CL
Down Bin 3600C: tCK(AVG) min
Down Bin 3600C: tCK(AVG) max
Down Bin 3600BN,B: tAAmin
Down Bin 3600BN,B: tRCDmin tRP-min
Down Bin 3600BN,B: Read CL
Down Bin 3600BN,B: tCK(AVG) min
Down Bin 3600BN,B: tCK(AVG) max
Down Bin 3600AN: tAAmin
Down Bin 3600AN: tRCDmin tRP-min
Down Bin 3600AN: Read CL
Down Bin 3600AN: tCK(AVG)
Down Bin 4000C: tAAmin
Down Bin 4000C: tRCDmin tRP-min
Down Bin 4000C: Read CL
Down Bin 4000C: tCK(AVG) min
Down Bin 4000C: tCK(AVG) max
Down Bin 4000BN,B: tAAmin
Down Bin 4000BN,B: tRCDmin tRP-min
Down Bin 4000BN,B: Read CL
Down Bin 4000BN,B: tCK(AVG) min
Down Bin 4000BN,B: tCK(AVG) max
Down Bin 4000AN: tAAmin
Down Bin 4000AN: tRCDmin tRP-min
Down Bin 4000AN: Read CL
Down Bin 4000AN: tCK(AVG)
Down Bin 4400C: tAAmin
Down Bin 4400C: tRCDmin tRP-min
Down Bin 4400C: Read CL
Down Bin 4400C: tCK(AVG) min
Down Bin 4400C: tCK(AVG) max
Down Bin 4400BN,B: tAAmin
Down Bin 4400BN,B: tRCDmin tRP-min
Down Bin 4400BN,B: Read CL
Down Bin 4400BN,B: tCK(AVG) min
Down Bin 4400BN,B: tCK(AVG) max
Down Bin 4400AN: tAAmin
Down Bin 4400AN: tRCDmin tRP-min
Down Bin 4400AN: Read CL
Down Bin 4400AN: tCK(AVG)
Supported CL
Specification section
Module Current measurement basis
Module section title
Module overall length (Front, outer)
Module length (Front, inner)
Module height / top dimension (Front)
Module height (Front)
Dimension (Front, vertical)
Contact field width segment (Front)
Component thickness / dimension (Detail E)
PCB thickness (Side view)
Module overall length (Back, outer)
Module length (Back, inner)
Side view height (max)
Component pitch / dimension (Side)
Dimension (Detail F)
Edge / chamfer radius
Dimension (Detail A area)
Pin reference
On-module component callout
Dimension (Detail B/D area)
Contact dimension (Detail of Contacts A, F)
Contact dimension (Detail of Contacts E)
Contact dimension (Detail of Contacts B)
Pin reference (Detail of Contacts B)
Contact dimension (Detail of Contacts C)
Pin reference (Detail of Contacts C)
Non-metalized keep out area callout (Detail of Contacts C)
Keep out dimension (Detail of Contacts C)
Contact dimension (Detail of Contacts D)
Non-metalized keep out area callout (Detail of Contacts D)
Keep out dimension (Detail of Contacts D)
Module length dimension (Back)
Units note
Voltage on VDD pin relative to Vss (VDD)
Voltage on VDDQ pin relative to Vss (VDDQ)
Voltage on VPP pin relative to Vss (VPP)
Voltage on any pin relative to Vss (VIN, VOUT)
Storage Temperature (TSTG)
Device Supply Voltage (VDD) Min
Device Supply Voltage (VDD) Typ
Device Supply Voltage (VDD) Max
Device Supply Voltage (VDD) Z(f) 2-10MHz Zmax
Device Supply Voltage (VDD) Z(f) 20MHz Zmax
Supply Voltage for I/O (VDDQ) Min
Supply Voltage for I/O (VDDQ) Typ
Supply Voltage for I/O (VDDQ) Max
Supply Voltage for I/O (VDDQ) Z(f) 2-10MHz Zmax
Supply Voltage for I/O (VDDQ) Z(f) 20MHz Zmax
Core Power Voltage (VPP) Min
Core Power Voltage (VPP) Typ
Core Power Voltage (VPP) Max
Core Power Voltage (VPP) Z(f) 2-10MHz Zmax
Core Power Voltage (VPP) Z(f) 20MHz Zmax
Rx Mask voltage - p-p (VciVW) Max
Rx Timing Window (TcIVW) Max
CA Input Pulse Amplitude (VIHL_AC) Max
CA Input Pulse Width (TcIPW)
Input Slew Rate over VcIVW (SRIN_cIVW) Min
Input Slew Rate over VcIVW (SRIN_cIVW) Max
REFab Normal tREFI1 (0C<=TCASE<=85C)
REFab Normal tREFI1 (85C<TCASE<=95C)
REFab Fine Granularity tREFI2 (0C<=TCASE<=85C)
REFab Fine Granularity tREFI2 (85C<TCASE<=95C)
REFsb Fine Granularity tREFIsb (0C<=TCASE<=85C)
REFsb Fine Granularity tREFIsb (85C<TCASE<=95C)
Baseline tREF refresh period
Refresh commands per tREF period
Normal Refresh (REFab) tRFC1(min) 16Gb
Fine Granularity Refresh (REFab) tRFC2(min) 16Gb
Same Bank Refresh (REFsb) tRFCsb(min) 16Gb
Same Bank Refresh to ACT delay tREFSBRD(min) 16Gb
Same Bank Refresh to ACT delay SLR tREFSBRD_slr(min) 16Gb
Same Bank Refresh to ACT delay DLR tREFSBRD_dlr(min) 16Gb
DRAM Reference clock frequency (tCK) Min
DRAM Reference clock frequency (tCK) Max
Duty Cycle Error (tCK_Duty_UI_Error) Max
Rj RMS value of 1-UI Jitter (tCK_1UI_Rj_NoBUJ) Max
Dj pp value of 1-UI Jitter (tCK_1UI_Dj_NoBUJ) Max
Tj value of 1-UI Jitter (tCK_1UI_Tj_NoBUJ) Max
Rj RMS value of N-UI Jitter N=2,3 (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter N=2,3 (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter N=2,3 (tCK_NUI_Tj_NoBUJ) Max
Rj RMS value of N-UI Jitter N=4..30 (tCK_NUI_Rj_NoBUJ) Max
Dj pp value of N-UI Jitter N=4..30 (tCK_NUI_Dj_NoBUJ) Max
Tj value of N-UI Jitter N=4..30 (tCK_NUI_Tj_NoBUJ) Max
Clock differential input crosspoint voltage ratio (VIX_CK_Ratio) Max
Input Clock Voltage Sensitivity differential pp (VRx_CK) Max
Differential input high measurement level CK_t, CK_c (VIHdiffCK)
Differential input low measurement level CK_t, CK_c (VILdiffCK)
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Min
Differential Input Slew Rate for CK_t, CK_c (SRIdiff_CK) Max
DQ Timing Width (tRx_DQ_tMargin) Min
Degradation of timing width with DCD injection in DQS (DtRx_DQ_tMargin_DQS_DCD) Max
Degradation of timing width with Rj injection in DQS (DtRx_DQ_tMargin_DQS_Rj) Max
Degradation of timing width with DCD and Rj injection in DQS (DtRx_DQ_tMargin_DQS_DCD_Rj) Max
Delay of any data lane relative to DQS crossing (tRx_DQS2DQ) Min
Delay of any data lane relative to DQS crossing (tRx_DQS2DQ) Max
Applied DCD to the DQS (tRx_DQS_DCD) Max
Applied Rj RMS to the DQS (tRx_DQS_Rj) Max
Applied DCD and Rj RMS to the DQS (tRx_DQS_DCD_Rj) Max
DQS Rx Input Voltage Sensitivity differential pp (VRx_DQS) Max
DQS differential input crosspoint voltage ratio (VIX_DQS_Ratio) Max
Differential input high measurement level DQS_t, DQS_c (VIHdiffDQS)
Differential input low measurement level DQS_t, DQS_c (VILdiffDQS)
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS)
Minimum DQ Rx input voltage sensitivity applied around Vref (VRx_DQ) Max
Eye height of stressed eye Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) Max
Eye width of stressed eye Golden Reference Channel 1 (RxEW_Stressed_Eye_Golden_Ref_Channel_1) Max
Vswing stress to meet above data eye (Vswing_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected sinusoidal jitter at 200 MHz (Sj_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected Random wide band (10 MHz-1 GHz) Jitter (Rj_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected Random wide band (10 MHz-1 GHz) Jitter (Rj_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected voltage noise PRBS23 / at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected voltage noise PRBS23 / at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max
Connectivity Test Mode tCT_IS Min
Connectivity Test Mode tCT_Enable Min
Connectivity Test Mode tCT_Valid Max
TEN AC Input High Voltage (VIH(AC)_TEN) Min
TEN AC Input High Voltage (VIH(AC)_TEN) Max
TEN DC Input High Voltage (VIH(DC)_TEN) Min
TEN DC Input High Voltage (VIH(DC)_TEN) Max
TEN DC Input Low Voltage (VIL(DC)_TEN) Min
TEN DC Input Low Voltage (VIL(DC)_TEN) Max
TEN AC Input Low Voltage (VIL(AC)_TEN) Min
TEN AC Input Low Voltage (VIL(AC)_TEN) Max
TEN Input signal Falling time (TF_input_TEN) Max
TEN Input signal Rising time (TR_input_TEN) Max
RESET_n AC Input High Voltage (VIH(AC)_RESET) Min
RESET_n AC Input High Voltage (VIH(AC)_RESET) Max
RESET_n DC Input High Voltage (VIH(DC)_RESET) Min
RESET_n DC Input High Voltage (VIH(DC)_RESET) Max
RESET_n DC Input Low Voltage (VIL(DC)_RESET) Min
RESET_n DC Input Low Voltage (VIL(DC)_RESET) Max
RESET_n AC Input Low Voltage (VIL(AC)_RESET) Min
RESET_n AC Input Low Voltage (VIL(AC)_RESET) Max
RESET_n Rising time (TR_RESET) Max
RESET pulse width (tPW_RESET) Min
Output Driver assumed RZQ
RON34Pd at VOLdc=0.5*VDDQ Min
RON34Pd at VOLdc=0.5*VDDQ Nom
RON34Pd at VOLdc=0.5*VDDQ Max
RON34Pd at VOMdc=0.8*VDDQ Min
RON34Pd at VOMdc=0.8*VDDQ Nom
RON34Pd at VOMdc=0.8*VDDQ Max
RON34Pd at VOHdc=0.95*VDDQ Min
RON34Pd at VOHdc=0.95*VDDQ Nom
RON34Pd at VOHdc=0.95*VDDQ Max
RON34Pu at VOLdc=0.5*VDDQ Min
RON34Pu at VOLdc=0.5*VDDQ Nom
RON34Pu at VOLdc=0.5*VDDQ Max
RON34Pu at VOMdc=0.8*VDDQ Min
RON34Pu at VOMdc=0.8*VDDQ Nom
RON34Pu at VOMdc=0.8*VDDQ Max
RON34Pu at VOHdc=0.95*VDDQ Min
RON34Pu at VOHdc=0.95*VDDQ Nom
RON34Pu at VOHdc=0.95*VDDQ Max
RON48Pd at VOLdc=0.5*VDDQ Min
RON48Pd at VOLdc=0.5*VDDQ Nom
RON48Pd at VOLdc=0.5*VDDQ Max
RON48Pd at VOMdc=0.8*VDDQ Min
RON48Pd at VOMdc=0.8*VDDQ Nom
RON48Pd at VOMdc=0.8*VDDQ Max
RON48Pd at VOHdc=0.95*VDDQ Min
RON48Pd at VOHdc=0.95*VDDQ Nom
RON48Pd at VOHdc=0.95*VDDQ Max
RON48Pu at VOLdc=0.5*VDDQ Min
RON48Pu at VOLdc=0.5*VDDQ Nom
RON48Pu at VOLdc=0.5*VDDQ Max
RON48Pu at VOMdc=0.8*VDDQ Min
RON48Pu at VOMdc=0.8*VDDQ Nom
RON48Pu at VOMdc=0.8*VDDQ Max
RON48Pu at VOHdc=0.95*VDDQ Min
RON48Pu at VOHdc=0.95*VDDQ Nom
RON48Pu at VOHdc=0.95*VDDQ Max
Mismatch between pull-up and pull-down (MMPuPd) at VOMdc=0.8*VDDQ Min
Mismatch between pull-up and pull-down (MMPuPd) at VOMdc=0.8*VDDQ Max
Mismatch DQ-DQ within byte variation pull-up (MMPudd) Max
Mismatch DQ-DQ within byte variation pull-dn (MMPddd) Max
Loopback RON34Pd at VOLdc=0.5*VDDQ Min
Loopback RON34Pd at VOLdc=0.5*VDDQ Nom
Loopback RON34Pd at VOLdc=0.5*VDDQ Max
Loopback RON34Pd at VOMdc=0.8*VDDQ Min
Loopback RON34Pd at VOMdc=0.8*VDDQ Max
Loopback RON34Pd at VOHdc=0.95*VDDQ Min
Loopback RON34Pd at VOHdc=0.95*VDDQ Max
Loopback RON34Pu at VOLdc=0.5*VDDQ Min
Loopback RON34Pu at VOLdc=0.5*VDDQ Max
Loopback RON34Pu at VOMdc=0.8*VDDQ Min
Loopback RON34Pu at VOMdc=0.8*VDDQ Max
Loopback RON34Pu at VOHdc=0.95*VDDQ Min
Loopback RON34Pu at VOHdc=0.95*VDDQ Max
Loopback Mismatch between pull-up and pull-down (MMPuPd) Min
Loopback Mismatch between pull-up and pull-down (MMPuPd) Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up (MMPudd) Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn (MMPddd) Max
Loopback LBDQS Output Low Time (tLBQSL) Min
Loopback LBDQS Output High Time (tLBQSH) Min
Loopback LBDQS to LBDQ Skew (tLBDQSQ) Min
Loopback LBDQ Output Time from LBDQS (tLBQH) Min
Loopback Data valid window (tLBDVW) Min
Alert_n RONPd at VOLdc=0.1*VDDQ Min
Alert_n RONPd at VOLdc=0.1*VDDQ Max
Alert_n RONPd at VOMdc=0.8*VDDQ Min
Alert_n RONPd at VOMdc=0.8*VDDQ Max
Alert_n RONPd at VOHdc=0.95*VDDQ Min
Alert_n RONPd at VOHdc=0.95*VDDQ Max
CT Mode RONPd_CT at VOBdc=0.2xVDDQ Max
CT Mode RONPd_CT at VOLdc=0.5xVDDQ Max
CT Mode RONPd_CT at VOMdc=0.8xVDDQ Max
CT Mode RONPd_CT at VOHdc=0.95xVDDQ Max
CT Mode RONPu_CT at VOBdc=0.2xVDDQ Max
CT Mode RONPu_CT at VOLdc=0.5xVDDQ Max
CT Mode RONPu_CT at VOMdc=0.8xVDDQ Max
CT Mode RONPu_CT at VOHdc=0.95xVDDQ Max
CT Mode uncalibrated drive strength tolerance
Single-ended Output high measurement level (VOH)
Single-ended Output low measurement level (VOL)
Loopback Single-ended Output high measurement level (VOH)
Loopback Single-ended Output low measurement level (VOL)
Single ended output slew rate (SRQse) Min
Single ended output slew rate (SRQse) Max
Differential output high measurement level (VOHdiff)
Differential output low measurement level (VOLdiff)
Differential output slew rate (SRQdiff) Min
Differential output slew rate (SRQdiff) Max
Rj RMS Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Rj_NoBUJ) Max
Dj pp Value of 1-UI Jitter without BUJ (tTx_DQS_1UI_Dj_NoBUJ) Max
Rj RMS Value of N-UI jitter without BUJ 1<N<4 (tTx_DQS_NUI_Rj_NoBUJ) Max
Dj pp Value of N-UI Jitter without BUJ 1<N<4 (tTx_DQS_NUI_Dj_NoBUJ) Max
Max value of tTx_DQS_Rj_1UI_NoBUJ and tTx_DQS_Rj_NUI_NoBUJ
Rj RMS of 1-UI jitter without BUJ (tTx_DQ_1UI_Rj_NoBUJ) Max
Dj pp 1-UI jitter without BUJ (tTx_DQ_1UI_Dj_NoBUJ) Max
Rj RMS of N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Rj_NoBUJ) Max
Dj pp N-UI jitter without BUJ 1<N<4 (tTx_DQ_NUI_Dj_NoBUJ) Max
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) Min
Delay of any data lane relative to strobe lane (tTx_DQS2DQ) Max
Max value of tTx_DQ_Rj_1UI_NoBUJ and tTx_DQ_Rj_NUI_NoBUJ
Eye Height at transmitter DQ-DQS skew 1UI (TxEH_DQ_SES_1UI) Min
Eye Width at transmitter DQ-DQS skew 1UI (TxEW_DQ_SES_1UI) Min
Eye Height at transmitter DQ-DQS skew 2UI (TxEH_DQ_SES_2UI) Min
Eye Width at transmitter DQ-DQS skew 2UI (TxEW_DQ_SES_2UI) Min
Eye Height at transmitter DQ-DQS skew 3UI (TxEH_DQ_SES_3UI) Min
Eye Width at transmitter DQ-DQS skew 3UI (TxEW_DQ_SES_3UI) Min
Eye Height at transmitter DQ-DQS skew 4UI (TxEH_DQ_SES_4UI) Min
Eye Width at transmitter DQ-DQS skew 4UI (TxEW_DQ_SES_4UI) Min
Eye Height at transmitter DQ-DQS skew 5UI (TxEH_DQ_SES_5UI) Min
Eye Width at transmitter DQ-DQS skew 5UI (TxEW_DQ_SES_5UI) Min
3DS DDR5-4400B Speed Bin CL-nRCD-nRP
3DS DDR5-4400B Read command to first data (tAA) min
3DS DDR5-4400B Read command to first data (tAA) max
3DS DDR5-4400B Activate to Read/Write delay (tRCD) min
3DS DDR5-4400B Row Precharge Time (tRP) min
3DS DDR5-4400B Activate to Precharge period (tRAS) min
3DS DDR5-4400B Activate to Precharge period (tRAS) max
3DS DDR5-4400B Activate to Activate/Refresh period (tRC) min
3DS DDR5-4400B CAS Write Latency (CWL)
3DS DDR5-4400B Supported CL
3DS DDR5-4800B Speed Bin CL-nRCD-nRP
3DS DDR5-4800B Read command to first data (tAA) min
3DS DDR5-4800B Read command to first data (tAA) max
3DS DDR5-4800B Activate to Read/Write delay (tRCD) min
3DS DDR5-4800B Row Precharge Time (tRP) min
3DS DDR5-4800B Activate to Precharge period (tRAS) min
3DS DDR5-4800B Activate to Precharge period (tRAS) max
3DS DDR5-4800B Activate to Activate/Refresh period (tRC) min
3DS DDR5-4800B CAS Write Latency (CWL)
3DS DDR5-4800B Supported CL
Rounding Algorithm correction factor (CorrFact)
Scaled correction factor (ScaledCorrFact)
3DS tAAmin range (from Speed Bin Tables and DIMM SPD bytes 30-31)
3DS tRCDtRPmin range (from Speed Bin Tables and DIMM SPD bytes 32-33)
Specification type
Module IDD note
General tolerance
Module overall length (Front)
Module length (Front inner)
Edge to first feature (Front, left)
Notch/feature dimension (Front, left vertical)
Module height (Front, right)
Height to feature 17.10 (Front, right)
Height to feature 14.10 (Front, right)
Height to feature 11.00 (Front, right)
Height to feature 8.00 (Front, right)
Contact/edge connector height (Front, left)
Pin 1 to first contact group dimension (Front)
Contact span left (Front)
Contact span right (Front)
Pin 1 callout (Front)
Pin 35 callout (Detail A, Front)
Pin 47 callout (Detail A, Front)
Pin 105 callout (Detail C, Front)
Pin 117 callout (Detail C, Front)
Component callout (Front)
Detail callouts (Front)
PCB thickness keep-out / feature (Back)
Corner radius (Back)
Component callout (Back)
Pin 39 callout (Detail B, Back)
Pin 51 callout (Detail B, Back)
Pin 110 callout (Detail C, Back)
Pin 122 callout (Detail C, Back)
Contact pad width (Detail of Contacts A, F)
Contact height (Detail of Contacts A, F)
Contact pitch (Detail of Contacts A, F)
Keep-out max 0.30 (Detail of Contacts A, F)
Keep-out max 0.25 (Detail of Contacts A, F)
Keep-out max 0.35 (Detail of Contacts A, F)
Non-metallized note (Detail of Contacts A, F)
Contact group width inner (Detail of Contacts B)
Contact group width outer (Detail of Contacts B)
Contact height left (Detail of Contacts B)
Contact height right (Detail of Contacts B)
Contact group width inner (Detail of Contacts C)
Contact group width outer (Detail of Contacts C)
Contact height left (Detail of Contacts C)
Contact height right (Detail of Contacts C)
Contact pad width (Detail of Contacts D)
Contact height (Detail of Contacts D)
Contact pitch (Detail of Contacts D)
Keep-out max 0.30 (Detail of Contacts D, left)
Keep-out max 0.30 (Detail of Contacts D, right)
Keep-out max 0.35 (Detail of Contacts D)
Non-metallized note (Detail of Contacts D)
Contact feature width (Detail of Contacts E)
Contact feature height (Detail of Contacts E)
Contact feature dimension 5.95 (Detail of Contacts E)
Contact feature dimension 1.50 (Detail of Contacts E)
Contact feature dimension 0.20 (Detail of Contacts E)
Contact feature dimension 0.2 (Detail of Contacts E)
Module thickness (Side)
PCB/feature thickness (Side)
Document revision/date
Default resistor value (block diagram)
DRAM ZQ pin resistor
VDD: Voltage on VDD pin relative to Vss
VDDQ: Voltage on VDDQ pin relative to Vss
VPP: Voltage on VPP pin relative to Vss
VIN, VOUT: Voltage on any pin relative to Vss
TSTG: Storage Temperature
VDD Device Supply Voltage
VDDQ Supply Voltage for I/O
VPP Core Power Voltage
tREFI baseline refresh period (tREF)
Normal Refresh (REFab) tRFC1(min)
Fine Granularity Refresh (REFab) tRFC2(min)
Same Bank Refresh (REFsb) tRFCsb(min)
3DS Normal Refresh same logical rank tRFC1_slr(min)
3DS Fine Granularity same logical rank tRFC2_slr(min)
3DS Same Bank Refresh same logical rank tRFCsb_slr(min)
3DS Normal Refresh different logical rank tRFC1_dlr(min)
3DS Normal Refresh different physical rank tRFC1_dpr(min)
3DS Fine Granularity different logical rank tRFC2_dlr(min)
3DS Fine Granularity different physical rank tRFC2_dpr(min)
3DS Same Bank Refresh different logical rank tRFCsb_dlr(min)
Same Bank Refresh to ACT delay tREFSBRD(min)
Same Bank Refresh to ACT delay SLR tREFSBRD_slr(min)
Same Bank Refresh to ACT delay DLR tREFSBRD_dlr(min)
Duty Cycle Error (tCK_Duty_UI_Error)
Input Clock Voltage Sensitivity (differential pp) (VRx_CK) Max
VIHdiffCK Differential input high measurement level (CK_t, CK_c)
VILdiffCK Differential input low measurement level (CK_t, CK_c)
Degradation of timing width with DCD injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD) Max
Degradation of timing width with Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_Rj) Max
Degradation of timing width with DCD and Rj injection in DQS (ΔtRx_DQ_tMargin_DQS_DCD_Rj) Max
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Min
Delay of any data lane relative to DQS_t/DQS_c crossing (tRx_DQS2DQ) Max
DQS Rx Input Voltage Sensitivity (differential pp) (VRx_DQS) Max
VIHdiffDQS Differential input high measurement level (DQS_t, DQS_c)
VILdiffDQS Differential input low measurement level (DQS_t, DQS_c)
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) Min
Differential Input Slew Rate for DQS_t, DQS_c (SRIdiff_DQS) Max
Eye height of stressed eye for Golden Reference Channel 1 (RxEH_Stressed_Eye_Golden_Ref_Channel_1) Max
Injected voltage noise PRBS23 or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Min
Injected voltage noise PRBS23 or at 2.1 GHz (Vnoise_Stressed_Eye_Golden_Ref_Channel_1) Max
Golden Reference Channel 1 Characteristics (Golden_Ref_Channel_1_Characteristics)
tCT_IS Min
tCT_Enable Min
tCT_Valid Max
AC Input High Voltage (VIH(AC)_RESET) Min
AC Input High Voltage (VIH(AC)_RESET) Max
DC Input High Voltage (VIH(DC)_RESET) Min
DC Input High Voltage (VIH(DC)_RESET) Max
DC Input Low Voltage (VIL(DC)_RESET) Min
DC Input Low Voltage (VIL(DC)_RESET) Max
AC Input Low Voltage (VIL(AC)_RESET) Min
AC Input Low Voltage (VIL(AC)_RESET) Max
Rising time (TR_RESET) Max
RON34Pd VOLdc=0.5*VDDQ Min
RON34Pd VOLdc=0.5*VDDQ Nom
RON34Pd VOLdc=0.5*VDDQ Max
RON34Pd VOMdc=0.8*VDDQ Min
RON34Pd VOMdc=0.8*VDDQ Nom
RON34Pd VOMdc=0.8*VDDQ Max
RON34Pd VOHdc=0.95*VDDQ Min
RON34Pd VOHdc=0.95*VDDQ Nom
RON34Pd VOHdc=0.95*VDDQ Max
RON34Pu VOLdc=0.5*VDDQ Min
RON34Pu VOLdc=0.5*VDDQ Nom
RON34Pu VOLdc=0.5*VDDQ Max
RON34Pu VOMdc=0.8*VDDQ Min
RON34Pu VOMdc=0.8*VDDQ Nom
RON34Pu VOMdc=0.8*VDDQ Max
RON34Pu VOHdc=0.95*VDDQ Min
RON34Pu VOHdc=0.95*VDDQ Nom
RON34Pu VOHdc=0.95*VDDQ Max
RON48Pd VOLdc=0.5*VDDQ Min
RON48Pd VOLdc=0.5*VDDQ Nom
RON48Pd VOLdc=0.5*VDDQ Max
RON48Pd VOMdc=0.8*VDDQ Min
RON48Pd VOMdc=0.8*VDDQ Nom
RON48Pd VOMdc=0.8*VDDQ Max
RON48Pd VOHdc=0.95*VDDQ Min
RON48Pd VOHdc=0.95*VDDQ Nom
RON48Pd VOHdc=0.95*VDDQ Max
RON48Pu VOLdc=0.5*VDDQ Min
RON48Pu VOLdc=0.5*VDDQ Nom
RON48Pu VOLdc=0.5*VDDQ Max
RON48Pu VOMdc=0.8*VDDQ Min
RON48Pu VOMdc=0.8*VDDQ Nom
RON48Pu VOMdc=0.8*VDDQ Max
RON48Pu VOHdc=0.95*VDDQ Min
RON48Pu VOHdc=0.95*VDDQ Nom
RON48Pu VOHdc=0.95*VDDQ Max
Mismatch between pull-up and pull-down MMPuPd (VOMdc=0.8*VDDQ) Min
Mismatch between pull-up and pull-down MMPuPd (VOMdc=0.8*VDDQ) Max
Mismatch DQ-DQ within byte variation pull-up MMPudd (VOMdc=0.8*VDDQ) Max
Mismatch DQ-DQ within byte variation pull-dn MMPddd (VOMdc=0.8*VDDQ) Max
Loopback RON34Pd VOLdc=0.5*VDDQ Min
Loopback RON34Pd VOLdc=0.5*VDDQ Nom
Loopback RON34Pd VOLdc=0.5*VDDQ Max
Loopback RON34Pd VOMdc=0.8*VDDQ Min
Loopback RON34Pd VOMdc=0.8*VDDQ Nom
Loopback RON34Pd VOMdc=0.8*VDDQ Max
Loopback RON34Pd VOHdc=0.95*VDDQ Min
Loopback RON34Pd VOHdc=0.95*VDDQ Nom
Loopback RON34Pd VOHdc=0.95*VDDQ Max
Loopback RON34Pu VOLdc=0.5*VDDQ Min
Loopback RON34Pu VOLdc=0.5*VDDQ Nom
Loopback RON34Pu VOLdc=0.5*VDDQ Max
Loopback RON34Pu VOMdc=0.8*VDDQ Min
Loopback RON34Pu VOMdc=0.8*VDDQ Nom
Loopback RON34Pu VOMdc=0.8*VDDQ Max
Loopback RON34Pu VOHdc=0.95*VDDQ Min
Loopback RON34Pu VOHdc=0.95*VDDQ Nom
Loopback RON34Pu VOHdc=0.95*VDDQ Max
Loopback Mismatch between pull-up and pull-down MMPuPd Min
Loopback Mismatch between pull-up and pull-down MMPuPd Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd Max
Loopback Data valid window (tLBQH-tLBDQSQ) per UI per DRAM (tLBDVW) Min
Alert_n RONPd (VOLdc=0.1*VDDQ) Min
Alert_n RONPd (VOLdc=0.1*VDDQ) Max
Alert_n RONPd (VOMdc=0.8*VDDQ) Min
Alert_n RONPd (VOMdc=0.8*VDDQ) Max
Alert_n RONPd (VOHdc=0.95*VDDQ) Min
Alert_n RONPd (VOHdc=0.95*VDDQ) Max
CT Mode RONPd_CT (VOBdc=0.2 x VDDQ) Max
CT Mode RONPd_CT (VOLdc=0.5 x VDDQ) Max
CT Mode RONPd_CT (VOMdc=0.8 x VDDQ) Max
CT Mode RONPd_CT (VOHdc=0.95 x VDDQ) Max
CT Mode RONPu_CT (VOBdc=0.2 x VDDQ) Max
CT Mode RONPu_CT (VOLdc=0.5 x VDDQ) Max
CT Mode RONPu_CT (VOMdc=0.8 x VDDQ) Max
CT Mode RONPu_CT (VOHdc=0.95 x VDDQ) Max
VOH Output high measurement level (for output SR)
VOL Output low measurement level (for output SR)
VOH Output high measurement level for Loopback Signals (for output SR)
VOL Output low measurement level for Loopback Signals (for output SR)
VOHdiff Differential output high measurement level (for output SR)
VOLdiff Differential output low measurement level (for output SR)
Tx DQS Rj max value note (1-UI and N-UI)
Tx DQ Rj max value note (1-UI and N-UI)
Eye Height at transmitter, DQ/DQS skew 1UI (TxEH_DQ_SES_1UI) Min
Eye Width at transmitter, DQ/DQS skew 1UI (TxEW_DQ_SES_1UI) Min
Eye Height at transmitter, DQ/DQS skew 2UI (TxEH_DQ_SES_2UI) Min
Eye Width at transmitter, DQ/DQS skew 2UI (TxEW_DQ_SES_2UI) Min
Eye Height at transmitter, DQ/DQS skew 3UI (TxEH_DQ_SES_3UI) Min
Eye Width at transmitter, DQ/DQS skew 3UI (TxEW_DQ_SES_3UI) Min
Eye Height at transmitter, DQ/DQS skew 4UI (TxEH_DQ_SES_4UI) Min
Eye Width at transmitter, DQ/DQS skew 4UI (TxEW_DQ_SES_4UI) Min
Eye Height at transmitter, DQ/DQS skew 5UI (TxEH_DQ_SES_5UI) Min
Eye Width at transmitter, DQ/DQS skew 5UI (TxEW_DQ_SES_5UI) Min
IDD measurement condition: IDD0
IDD measurement condition: IDDQ0
IDD measurement condition: IPP0
IDD measurement condition: IDD0F
IDD measurement condition: IDDQ0F
IDD measurement condition: IPP0F
IDD measurement condition: IDD2N
IDD measurement condition: IDDQ2N
IDD measurement condition: IPP2N
IDD measurement condition: IDD2NT
IDD measurement condition: IDDQ2NT
IDD measurement condition: IPP2NT
IDD measurement condition: IDD2P
IDD measurement condition: IDDQ2P
IDD measurement condition: IPP2P
IDD measurement condition: IDD3N
IDD measurement condition: IDDQ3N
IDD measurement condition: IPP3N
IDD measurement condition: IDD3P
IDD measurement condition: IDDQ3P
IDD measurement condition: IPP3P
IDD measurement condition: IDD4R
IDD measurement condition: IDD4RC
IDD measurement condition: IDDQ4R
IDD measurement condition: IPP4R
IDD measurement condition: IDD4W
IDD measurement condition: IDD4WC
IDD measurement condition: IDDQ4W
IDD measurement condition: IPP4W
IDD measurement condition: IDD5B
IDD measurement condition: IDDQ5B
IDD measurement condition: IPP5B
IDD measurement condition: IDD5F
IDD measurement condition: IDDQ5F
IDD measurement condition: IPP5F
IDD measurement condition: IDD5C
IDD measurement condition: IDDQ5C
IDD measurement condition: IPP5C
IDD measurement condition: IDD6N
IDD measurement condition: IDDQ6N
IDD measurement condition: IPP6N
IDD measurement condition: IDD6E
IDD measurement condition: IDDQ6E
IDD measurement condition: IPP6E
IDD measurement condition: IDD7
IDD measurement condition: IDDQ7
IDD measurement condition: IPP7
IDD measurement condition: IDD8
IDD measurement condition: IDDQ8
IDD measurement condition: IPP8
IDD measurement condition: IDD9
IDD measurement condition: IDDQ9
IDD measurement condition: IPP9
Burst Length (IDD measurement)
Section title
Table 1 title
Read command to first data (tAA) min
Read command to first data (tAA) max
Activate to Read or Write command delay time (tRCD) min
Row Precharge Time (tRP) min
Activate to Precharge command period (tRAS) min
Activate to Precharge command period (tRAS) max
Activate to Activate or Refresh command period (tRC) min
Down bin: Read CL
Down bin tAAmin (ns)
Down bin tCK(AVG) min
Down bin tCK(AVG) max
Down bin 3200C: tAAmin / tRCDtRPmin / Read CL
Down bin 3200BN,B: tAAmin / tRCDtRPmin / Read CL
Down bin 3200AN: tAAmin / tRCDtRPmin / Read CL
Down bin 3600C: tAAmin / tRCDtRPmin / Read CL
Down bin 3600BN,B: tAAmin / tRCDtRPmin / Read CL
Down bin 3600AN: tAAmin / tRCDtRPmin / Read CL
Down bin 4000C: tAAmin / tRCDtRPmin / Read CL
Down bin 4000BN,B: tAAmin / tRCDtRPmin / Read CL
Down bin 4000AN: tAAmin / tRCDtRPmin / Read CL
Down bin 4400C: tAAmin / tRCDtRPmin / Read CL
Down bin 4400BN,B: tAAmin / tRCDtRPmin / Read CL
Down bin 4400AN: tAAmin / tRCDtRPmin / Read CL
Table 2 title
Down bin 4800C: tAAmin / tRCDtRPmin / Read CL
Down bin 4800BN: tAAmin / tRCDtRPmin / Read CL
Down bin 4800B: tAAmin / tRCDtRPmin / Read CL
Down bin 4800AN: tAAmin / tRCDtRPmin / Read CL
Speed Bin Table Note 1
Speed Bin Table Note 4
Speed Bin Table Note 6
Speed Bin Table Note 7
Speed Bin Table Note 9
Speed Bin Table Note 12
tAAmin targets (MONO / 3DS)
tRCDtRPmin targets (MONO / 3DS)
3DS BinAN_tAAtarg
3DS BinB__tAAtarg
3DS BinBN_tAAtarg
3DS BinC__tAAtarg
3DS BinAN_tRCDtRPtarg
3DS BinBN_tRCDtRPtarg
3DS BinC__tRCDtRPtarg
3DS BinB__tRCDtRPtarg (faster than 3600)
3DS BinB__tRCDtRPtarg (3600 and slower)
Module Current note
General tolerance on all dimensions unless otherwise stated
Module overall length (outer)
Module length (inner reference)
Module overall length (back, outer)
Module length (back, inner reference)
Contact field dimension (left segment)
Contact field dimension (right segment)
Key / notch offset dimension
Detail A dimension
Detail E dimension
Edge / chamfer dimension
Corner radius (2x)
Notch / keepout dimension
Component callout
Detail B / C dimension
Detail of Contacts A, F dimension
Detail of Contacts E dimension
Detail of Contacts B - pin reference
Detail of Contacts B dimension
Detail of Contacts C - pin reference
Detail of Contacts C dimension
Detail of Contacts D dimension
Detail of Contacts D - non-metalized keep out area max
Detail of Contacts D - keep out area max
Detail of Contacts C - non-metalized keep out area max
Detail of Contacts C - keep out area max
Detail F dimension
Contact pitch
Side view - module thickness max
DRAM VDD/VDDQ
DRAM VPP
Bank configuration (x4/x8)
Bank configuration (x16)
Bank Groups (config)
Burst Length support
CRC
Revision
Pin description: CA0_A - CA6_A
Pin description: CA0_B - CA6_B
Pin description: CS0_A_n - CS1_A_n
Pin description: CS0_B_n - CS1_B_n
Pin description: DQ0_A - DQ31_A
Pin description: DQ0_B - DQ31_B
Pin description: CB0_A - CB7_A
Pin description: CB0_B - CB7_B
Pin description: TDQS0_A_t-TDQS9_A_t
Pin description: TDQS0_B_t-TDQS9_B_t
Pin description: TDQS0_A_c-TDQS9_A_c
Pin description: TDQS0_B_c-TDQS9_B_c
Pin description: DQS0_A_t - DQS9_A_t
Pin description: DQS0_B_t - DQS9_B_t
Pin description: DQS0_A_c - DQS9_A_c
Pin description: DQS0_B_c - DQS9_B_c
Pin description: PAR_A
Pin description: PAR_B
Pin description: RSP_A_n
Pin description: RSP_B_n
Pin description: VIN_BULK
Pin description: VSS
Pin description: VIN_MGMT
Pin description: PWR_GOOD / FAIL_n
Pin description: SCL
Pin description: ALERT_n
Pin description: SDA
Pin description: RESET_n
Pin description: SAA
Pin description: LBD
Pin description: CK_t
Pin description: LBS
Pin description: CK_c
Pin description: RFU
I/O functional: CK_t, CK_c
I/O functional: CA0_A-CA6_A, CA0_B-CA6_B, PAR_A, PAR_B
I/O functional: CS0_A_n-CS1_A_n, CS0_B_n-CS1_B_n
I/O functional: DQ0_A-DQ31_A, DQ0_B-DQ31_B
I/O functional: CB0_A-CB7_A, CB0_B-CB7_B
I/O functional: DQS0_A_t-DQS9_A_t, DQS0_A_c-DQS9_A_c, DQS0_B_t-DQS9_B_t, DQS0_B_c-DQS9_B_c
I/O functional: TDQS0_A_c-DQS9_A_c, TDQS0_B_c-DQS9_B_c
I/O functional: DM0_A_n-DM3_A_n, DM0_B_n-DM3_B_n
I/O functional: LBDQ
I/O functional: LBDQS
I/O functional: ALERT_n
I/O functional: RESET_n
I/O functional: SCL
I/O functional: SDA
I/O functional: SAA
I/O functional: RFU
I/O functional: PWR_GOOD
I/O functional: VIN_MGMT
I/O functional: VIN_BULK
I/O functional: VSS
Pin assignment table
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VPP pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Device Supply Voltage VDD (Min)
Device Supply Voltage VDD (Typ)
Device Supply Voltage VDD (Max)
VDD Z(f) Spec Freq: 2MHz to 10MHz (Zmax)
VDD Z(f) Spec Freq: 20MHz (Zmax)
Supply Voltage for I/O VDDQ (Min)
Supply Voltage for I/O VDDQ (Typ)
Supply Voltage for I/O VDDQ (Max)
VDDQ Z(f) Spec Freq: 2MHz to 10MHz (Zmax)
VDDQ Z(f) Spec Freq: 20MHz (Zmax)
Core Power Voltage VPP (Min)
Core Power Voltage VPP (Typ)
Core Power Voltage VPP (Max)
VPP Z(f) Spec Freq: 2MHz to 10MHz (Zmax)
VPP Z(f) Spec Freq: 20MHz (Zmax)
Rx Mask voltage - p-p (VcIVW) Max @ DDR5-3200
Rx Mask voltage - p-p (VcIVW) Max @ DDR5-3600
Rx Mask voltage - p-p (VcIVW) Max @ DDR5-4000
Rx Mask voltage - p-p (VcIVW) Max @ DDR5-4400
Rx Mask voltage - p-p (VcIVW) Max @ DDR5-4800
Rx Timing Window (TcIVW) Max @ DDR5-3200
Rx Timing Window (TcIVW) Max @ DDR5-3600
Rx Timing Window (TcIVW) Max @ DDR5-4000
Rx Timing Window (TcIVW) Max @ DDR5-4400
Rx Timing Window (TcIVW) Max @ DDR5-4800
CA Input Pulse Amplitude (VIHL_AC) Max @ DDR5-3200
CA Input Pulse Amplitude (VIHL_AC) Max @ DDR5-3600
CA Input Pulse Amplitude (VIHL_AC) Max @ DDR5-4000
CA Input Pulse Amplitude (VIHL_AC) Max @ DDR5-4400
CA Input Pulse Amplitude (VIHL_AC) Max @ DDR5-4800
CA Input Pulse Width (TcIPW) @ DDR5-3200
CA Input Pulse Width (TcIPW) @ DDR5-3600
CA Input Pulse Width (TcIPW) @ DDR5-4000
CA Input Pulse Width (TcIPW) @ DDR5-4400
CA Input Pulse Width (TcIPW) @ DDR5-4800
Input Slew Rate over VcIVW (SRIN_cIVW) Min @ DDR5-3200
Input Slew Rate over VcIVW (SRIN_cIVW) Max @ DDR5-3200
Input Slew Rate over VcIVW (SRIN_cIVW) Min @ DDR5-3600
Input Slew Rate over VcIVW (SRIN_cIVW) Max @ DDR5-3600
Input Slew Rate over VcIVW (SRIN_cIVW) Min @ DDR5-4000
Input Slew Rate over VcIVW (SRIN_cIVW) Max @ DDR5-4000
Input Slew Rate over VcIVW (SRIN_cIVW) Min @ DDR5-4400
Input Slew Rate over VcIVW (SRIN_cIVW) Max @ DDR5-4400
Input Slew Rate over VcIVW (SRIN_cIVW) Min @ DDR5-4800
Input Slew Rate over VcIVW (SRIN_cIVW) Max @ DDR5-4800
tREFI1 (REFab, Normal, 0C<=TCASE<=85C) Expression
tREFI1 (REFab, Normal, 0C<=TCASE<=85C) Value
tREFI1 (REFab, Normal, 85C<TCASE<=95C) Expression
tREFI1 (REFab, Normal, 85C<TCASE<=95C) Value
tREFI2 (REFab, Fine Granularity, 0C<=TCASE<=85C) Expression
tREFI2 (REFab, Fine Granularity, 0C<=TCASE<=85C) Value
tREFI2 (REFab, Fine Granularity, 85C<TCASE<=95C) Expression
tREFI2 (REFab, Fine Granularity, 85C<TCASE<=95C) Value
tREFIsb (REFsb, Fine Granularity, 0C<=TCASE<=85C) Expression
tREFIsb (REFsb, Fine Granularity, 0C<=TCASE<=85C) Value
tREFIsb (REFsb, Fine Granularity, 85C<TCASE<=95C) Expression
tREFIsb (REFsb, Fine Granularity, 85C<TCASE<=95C) Value
Normal Refresh (REFab) tRFC1(min) @ 16Gb
Fine Granularity Refresh (REFab) tRFC2(min) @ 16Gb
Same Bank Refresh (REFsb) tRFCsb(min) @ 16Gb
Normal Refresh with 3DS same logical rank tRFC1_slr(min)
Fine Granularity Refresh with 3DS same logical rank tRFC2_slr(min)
Same Bank Refresh with 3DS same logical rank tRFCsb_slr(min)
Normal Refresh with 3DS different logical rank tRFC1_dlr(min)
Normal Refresh with 3DS different physical rank tRFC1_dpr(min)
Fine Granularity Refresh with 3DS different logical rank tRFC2_dlr(min)
Fine Granularity Refresh with 3DS different physical rank tRFC2_dpr(min)
Same Bank Refresh with 3DS different logical rank tRFCsb_dlr(min)
Same Bank Refresh to ACT delay tREFSBRD(min) @ 16Gb
Same Bank Refresh to ACT delay SLR tREFSBRD_slr(min) @ 16Gb
Same Bank Refresh to ACT delay DLR tREFSBRD_dlr(min) @ 16Gb
RON34Pd, VOLdc=0.5*VDDQ, Min
RON34Pd, VOLdc=0.5*VDDQ, Nom
RON34Pd, VOLdc=0.5*VDDQ, Max
RON34Pd, VOMdc=0.8*VDDQ, Min
RON34Pd, VOMdc=0.8*VDDQ, Nom
RON34Pd, VOMdc=0.8*VDDQ, Max
RON34Pd, VOHdc=0.95*VDDQ, Min
RON34Pd, VOHdc=0.95*VDDQ, Nom
RON34Pd, VOHdc=0.95*VDDQ, Max
RON34Pu, VOLdc=0.5*VDDQ, Min
RON34Pu, VOLdc=0.5*VDDQ, Nom
RON34Pu, VOLdc=0.5*VDDQ, Max
RON34Pu, VOMdc=0.8*VDDQ, Min
RON34Pu, VOMdc=0.8*VDDQ, Nom
RON34Pu, VOMdc=0.8*VDDQ, Max
RON34Pu, VOHdc=0.95*VDDQ, Min
RON34Pu, VOHdc=0.95*VDDQ, Nom
RON34Pu, VOHdc=0.95*VDDQ, Max
RON48Pd, VOLdc=0.5*VDDQ, Min
RON48Pd, VOLdc=0.5*VDDQ, Nom
RON48Pd, VOLdc=0.5*VDDQ, Max
RON48Pd, VOMdc=0.8*VDDQ, Min
RON48Pd, VOMdc=0.8*VDDQ, Nom
RON48Pd, VOMdc=0.8*VDDQ, Max
RON48Pd, VOHdc=0.95*VDDQ, Min
RON48Pd, VOHdc=0.95*VDDQ, Nom
RON48Pd, VOHdc=0.95*VDDQ, Max
RON48Pu, VOLdc=0.5*VDDQ, Min
RON48Pu, VOLdc=0.5*VDDQ, Nom
RON48Pu, VOLdc=0.5*VDDQ, Max
RON48Pu, VOMdc=0.8*VDDQ, Min
RON48Pu, VOMdc=0.8*VDDQ, Nom
RON48Pu, VOMdc=0.8*VDDQ, Max
RON48Pu, VOHdc=0.95*VDDQ, Min
RON48Pu, VOHdc=0.95*VDDQ, Nom
RON48Pu, VOHdc=0.95*VDDQ, Max
Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ, Min
Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte variation pull-up MMPudd, VOMdc=0.8*VDDQ, Max
Mismatch DQ-DQ within byte variation pull-dn MMPddd, VOMdc=0.8*VDDQ, Max
Loopback RON34Pd, VOLdc=0.5*VDDQ, Min
Loopback RON34Pd, VOLdc=0.5*VDDQ, Nom
Loopback RON34Pd, VOLdc=0.5*VDDQ, Max
Loopback RON34Pd, VOMdc=0.8*VDDQ, Min
Loopback RON34Pd, VOMdc=0.8*VDDQ, Nom
Loopback RON34Pd, VOMdc=0.8*VDDQ, Max
Loopback RON34Pd, VOHdc=0.95*VDDQ, Min
Loopback RON34Pd, VOHdc=0.95*VDDQ, Nom
Loopback RON34Pd, VOHdc=0.95*VDDQ, Max
Loopback RON34Pu, VOLdc=0.5*VDDQ, Min
Loopback RON34Pu, VOLdc=0.5*VDDQ, Nom
Loopback RON34Pu, VOLdc=0.5*VDDQ, Max
Loopback RON34Pu, VOMdc=0.8*VDDQ, Min
Loopback RON34Pu, VOMdc=0.8*VDDQ, Nom
Loopback RON34Pu, VOMdc=0.8*VDDQ, Max
Loopback RON34Pu, VOHdc=0.95*VDDQ, Min
Loopback RON34Pu, VOHdc=0.95*VDDQ, Nom
Loopback RON34Pu, VOHdc=0.95*VDDQ, Max
Loopback Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ, Min
Loopback Mismatch between pull-up and pull-down MMPuPd, VOMdc=0.8*VDDQ, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-up MMPudd, VOMdc=0.8*VDDQ, Max
Loopback Mismatch LBDQS-LBDQ within device variation pull-dn MMPddd, VOMdc=0.8*VDDQ, Max
tLBQSL (Loopback LBDQS Output Low Time), DDR5-3200, MIN
tLBQSH (Loopback LBDQS Output High Time), DDR5-3200, MIN
tLBDQSQ (Loopback LBDQS to LBDQ Skew), DDR5-3200, MIN
tLBQH (Loopback LBDQ Output Time from LBDQS), DDR5-3200, MIN
tLBDVW (Loopback Data valid window (tLBQH-tLBDQSQ) of each UI per DRAM), DDR5-3200, MIN
Alert_n RONPd, VOLdc=0.1*VDDQ, Min
Alert_n RONPd, VOLdc=0.1*VDDQ, Max
Alert_n RONPd, VOMdc=0.8*VDDQ, Min
Alert_n RONPd, VOMdc=0.8*VDDQ, Max
Alert_n RONPd, VOHdc=0.95*VDDQ, Min
Alert_n RONPd, VOHdc=0.95*VDDQ, Max
CT Mode RONPu_CT, VOBdc=0.2xVDDQ, Max
CT Mode RONPu_CT, VOLdc=0.5xVDDQ, Max
CT Mode RONPu_CT, VOMdc=0.8xVDDQ, Max
CT Mode RONPu_CT, VOHdc=0.95xVDDQ, Max
Single-ended VOH (Output high measurement level for output SR), DDR5-3200-6400
Single-ended VOL (Output low measurement level for output SR), DDR5-3200-6400
Loopback Single-ended VOH (Output high measurement level for output SR), DDR5-3200-6400
Loopback Single-ended VOL (Output low measurement level for output SR), DDR5-3200-6400
SRQse (Single ended output slew rate), DDR5-3200, MIN
SRQse (Single ended output slew rate), DDR5-3200, MAX
Differential VOHdiff (Differential output high measurement level for output SR), DDR5-3200-6400
Differential VOLdiff (Differential output low measurement level for output SR), DDR5-3200-6400
SRQdiff (Differential output slew rate), DDR5-3200, MIN
SRQdiff (Differential output slew rate), DDR5-3200, MAX
Speed Bin (DDR5-4400 table headline)
CL-nRCD-nRP (DDR5-4400B 3DS)
Activate to Read or Write command delay time (tRCD) max
Row Precharge Time (tRP) max
Activate to Activate or Refresh command period (tRC) max
Supported CL (DDR5-4400 3DS)
Down bin 1980 MT/s tAAmin
Down bin 1980 Read CL
Down bin 1980 tCK(AVG) min
Down bin 1980 tCK(AVG) max
Down bin 3200C tAAmin
Down bin 3200C tRCDmin tRPmin
Down bin 3200C Read CL
Down bin 3200C tCK(AVG) min
Down bin 3200C tCK(AVG) max
Down bin 3200BN,B tAAmin
Down bin 3200BN,B tRCDmin tRPmin
Down bin 3200BN,B Read CL
Down bin 3200BN,B tCK(AVG) min
Down bin 3200BN,B tCK(AVG) max
Down bin 3200AN tAAmin
Down bin 3200AN tRCDmin tRPmin
Down bin 3200AN Read CL
Down bin 3200AN tCK(AVG)
Down bin 3600C tAAmin
Down bin 3600C tRCDmin tRPmin
Down bin 3600C Read CL
Down bin 3600C tCK(AVG) min
Down bin 3600C tCK(AVG) max
Down bin 3600BN,B tAAmin
Down bin 3600BN,B tRCDmin tRPmin
Down bin 3600BN,B Read CL
Down bin 3600BN,B tCK(AVG) min
Down bin 3600BN,B tCK(AVG) max
Down bin 3600AN tAAmin
Down bin 3600AN tRCDmin tRPmin
Down bin 3600AN Read CL
Down bin 3600AN tCK(AVG)
Down bin 4000C tAAmin
Down bin 4000C tRCDmin tRPmin
Down bin 4000C Read CL
Down bin 4000C tCK(AVG) min
Down bin 4000C tCK(AVG) max
Down bin 4000BN,B tAAmin
Down bin 4000BN,B tRCDmin tRPmin
Down bin 4000BN,B Read CL
Down bin 4000BN,B tCK(AVG) min
Down bin 4000BN,B tCK(AVG) max
Down bin 4000AN tAAmin
Down bin 4000AN tRCDmin tRPmin
Down bin 4000AN Read CL
Down bin 4000AN tCK(AVG)
Down bin 4400C tAAmin
Down bin 4400C tRCDmin tRPmin
Down bin 4400C Read CL
Down bin 4400C tCK(AVG) min
Down bin 4400C tCK(AVG) max
Down bin 4400BN,B tAAmin
Down bin 4400BN,B tRCDmin tRPmin
Down bin 4400BN,B Read CL
Down bin 4400BN,B tCK(AVG) min
Down bin 4400BN,B tCK(AVG) max
Down bin 4400AN tAAmin
Down bin 4400AN tRCDmin tRPmin
Down bin 4400AN Read CL
Down bin 4400AN tCK(AVG)
Speed Bin (DDR5-4800 table headline)
CL-nRCD-nRP (DDR5-4800B 3DS)
Read command to first data (tAA) min (4800B)
Read command to first data (tAA) max (4800B)
Activate to Read or Write command delay time (tRCD) min (4800B)
Activate to Read or Write command delay time (tRCD) max (4800B)
Row Precharge Time (tRP) min (4800B)
Row Precharge Time (tRP) max (4800B)
Activate to Precharge command period (tRAS) min (4800B)
Activate to Precharge command period (tRAS) max (4800B)
Activate to Activate or Refresh command period (tRC) min (4800B)
Activate to Activate or Refresh command period (tRC) max (4800B)
CAS Write Latency (CWL) (4800B)
Supported CL (DDR5-4800 3DS)
Down bin 4800C tAAmin
Down bin 4800C tRCDmin tRPmin
Down bin 4800C Read CL
Down bin 4800C tCK(AVG) min
Down bin 4800C tCK(AVG) max
Down bin 4800BN tAAmin
Down bin 4800BN tRCDmin tRPmin
Down bin 4800BN Read CL
Down bin 4800BN tCK(AVG) min
Down bin 4800BN tCK(AVG) max
Down bin 4800B tAAmin
Down bin 4800B tRCDmin tRPmin
Down bin 4800B Read CL
Down bin 4800B tCK(AVG) min
Down bin 4800B tCK(AVG) max
Down bin 4800AN tAAmin
Down bin 4800AN tRCDmin tRPmin
Down bin 4800AN Read CL
Down bin 4800AN tCK(AVG)
Specification table
Drawing title
Module overall width
Module width (inner dimension)
Dimension (back, height)
Front segment width
Dimension
Notch/key dimension
Dimension (back)
Side thickness (max)
Component dimension
Registering Clock Driver location dimension
SPD/TS location dimension
Contact dimension
Contact pin reference
Keep-out note
Keep-out max dimension
Component label
Dimension tolerance note