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HMAA8GR7CJR4N (SK hynix)
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| Memory Class | rdimm |
|---|---|
| Die Density Gb | 16 |
| Registered | true |
| Pin Count | 288 |
| Voltage Vdd V | 1.2 |
| Memory Generation | ddr4 |
| Capacity Gb | 64 |
| Height Mm | 30.75 |
| Rank Organization | 2Rank of x4 |
| Ecc | Supports ECC error correction and detection |
| Speed Mt S | 1600 |
| Product Name | DDR4 SDRAM Registered DIMM Based on 16Gb C-die |
| Bank Address In A Bg | |
| Bg Address | |
| Ca Parity | |
| Cas Latency | |
| Cl Nrcd Nrp | |
| Cl Trcd Trp | |
| Column Address |
| Component Composition |
|---|
| Corner Radius |
|---|
| Data Transfer Rates |
|---|
| Die Type |
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| Document Revision |
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| General Tolerance Note |
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| Idd0 |
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| Idd0a |
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| Idd1 |
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| Idd1a |
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| Idd2n |
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| Idd2na |
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| Idd2nd |
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| Idd2ng |
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| Idd2nl |
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| Idd2np |
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| Idd2nt |
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| Idd2p |
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| Idd2q |
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| Idd3n |
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| Idd3na |
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| Idd3p |
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| Idd4r |
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| Idd4ra |
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| Idd4w |
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| Idd4wa |
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| Idd4wc |
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| Idd4wp |
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| Idd5b |
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| Idd5f2 |
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| Idd5f4 |
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| Idd6a |
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| Idd6e |
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| Idd6n |
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| Idd6r |
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| Idd7 |
|---|
| Idd8 |
|---|
| Internal Banks |
|---|
| Ipp0 |
|---|
| Ipp1 |
|---|
| Ipp2n |
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| Ipp2p |
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| Ipp3n |
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| Ipp3p |
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| Ipp4r |
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| Ipp4w |
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| Ipp5f2 |
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| Ipp5f4 |
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| Ipp6a |
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| Ipp6e |
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| Ipp6n |
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| Ipp6r |
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| Ipp7 |
|---|
| Ipp8 |
|---|
| Module Description |
|---|
| Of Bank Groups |
|---|
| Of Ranks |
|---|
| Pin Number Callout |
|---|
| Pre Fetch |
|---|
| Product Type |
|---|
| Row Address |
|---|
| Tck |
|---|
| Temperature Sensor |
|---|
| Tras |
|---|
| Trc |
|---|
| Trcd |
|---|
| Trp |
|---|
| Units |
|---|
| Vddq |
|---|
| Vddspd |
|---|
| Voltage Vpp V |
|---|
| Write Crc |
|---|
| Operating temp min (°C) | 0 |
|---|---|
| Operating temp max (°C) | 85 |
| SKU | HMAA8GR7CJR4N |
|---|
| Die / process base | |
|---|---|
| Document date | |
| Manufacturer | |
| Configuration / Density | |
| Rank Address | |
| Page size | |
| Downbinning note | |
| VDD Supply Voltage | |
| VPP Supply Voltage (SDRAM Activating Power Supply) | |
| VTT Supply | |
| 12V Supply | |
| VDDSPD Supply | |
| VREFCA Supply | |
| PC4 VDD Note | |
| VSS Supply | |
| Memory Data Bus | |
| ECC Check Bits | |
| RESET_n Operating Voltage Note | |
| Diagram type | |
| Module organization | |
| Revision | |
| Register present | |
| Address/Command/Control lines legend | |
| Board side label | |
| Note 1 (page1) - CK0 termination | |
| Note 2 (page1) - CK1 termination | |
| Note 3 (page1) - default resistor value | |
| Module description (page2) | |
| Note 1 (page2) - default resistor value | |
| Note 2 (page2) - net structure reference | |
| Note 3 (page2) - ZQ resistor value | |
| Note 4 (page2) - DRAM TEN pin | |
| Note 5 (page2) - VDDSPD routing | |
| Note 6 (page2) - VREFCA routing | |
| Module description (page3) | |
| SPD/thermal sensor present | |
| Register designator | |
| RCD pull-up resistor | |
| SPD address pins | |
| Note 1 (page3) - default resistor value | |
| Note 2 (page3) - net structure reference | |
| Note 3 (page3) - ZQ resistor value | |
| Note 4 (page3) - DRAM TEN pin | |
| Note 5 (page3) - VDDSPD routing | |
| Note 6 (page3) - VREFCA routing | |
| Total SDRAM count | |
| DQ data width | |
| Check-bit lanes | |
| VDD - Voltage on VDD pin relative to Vss | |
| VDDQ - Voltage on VDDQ pin relative to Vss | |
| VPP - Voltage on VPP pin relative to Vss | |
| VIN, VOUT - Voltage on any pin except VREFCA relative to Vss | |
| TSTG - Storage Temperature | |
| TOPER - Normal Operating Temperature Range | |
| TOPER - Extended Temperature Range | |
| VDD - Supply Voltage | |
| VDDQ - Supply Voltage for Output | |
| VPP - Supply Voltage for DRAM Activating | |
| VIH.CA(DC75) DC input logic high | |
| VIL.CA(DC75) DC input logic low | |
| VIH.CA(AC100) AC input logic high | |
| VIL.CA(AC100) AC input logic low | |
| VREFCA(DC) Reference Voltage for ADD, CMD inputs | |
| VIHdiff differential input high | |
| VILdiff differential input low | |
| tDVAC for CK_t - CK_c @ |VIH/Ldiff(AC)|=200mV (min) | |
| VSEH Single-ended high-level for CK_t, CK_c | |
| VSEL Single-ended low-level for CK_t, CK_c | |
| Maximum peak amplitude above VDD Absolute Max allowed for overshoot area (Addr/Cmd/Ctrl) | |
| Delta value between VDD Absolute Max and VDD Max allowed for overshoot area (Addr/Cmd/Ctrl) | |
| Maximum peak amplitude allowed for undershoot area (Addr/Cmd/Ctrl) | |
| Maximum overshoot area per 1tCK Above Absolute Max (Addr/Cmd/Ctrl) | |
| Maximum overshoot area per 1tCK Between Absolute Max and VDD Max (Addr/Cmd/Ctrl) | |
| Maximum undershoot area per 1tCK Below VSS (Addr/Cmd/Ctrl) | |
| Maximum peak amplitude above VDD Absolute Max allowed for overshoot area (Clock) | |
| Delta value between VDD Absolute Max and VDD Max allowed for overshoot area (Clock) | |
| Maximum peak amplitude allowed for undershoot area (Clock) | |
| Maximum overshoot area per 1UI Above Absolute Max (Clock) | |
| Maximum overshoot area per 1UI Between Absolute Max and VDD Max (Clock) | |
| Maximum undershoot area per 1UI Below VSS (Clock) | |
| Maximum peak amplitude above Max absolute level of Vin,Vout (DQ/DQS/DM) | |
| Overshoot area Between Max Absolute level of Vin,Vout and VDDQ Max | |
| Undershoot area Between Min absolute level of Vin,Vout and VDDQ Max | |
| Maximum peak amplitude below Min absolute level of Vin,Vout | |
| Maximum overshoot area per 1UI Above Max absolute level of Vin,Vout | |
| Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and VDDQ Max | |
| Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and VSSQ | |
| Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout | |
| VIX(CK) Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c | |
| VIX(CK) intermediate min limit (area dependent) | |
| VIX(CK) intermediate max limit (area dependent) | |
| VIH(AC)_RESET AC Input High Voltage | |
| VIH(DC)_RESET DC Input High Voltage | |
| VIL(DC)_RESET DC Input Low Voltage | |
| VIL(AC)_RESET AC Input Low Voltage | |
| TR_RESET Rising time | |
| tPW_RESET RESET pulse width | |
| VIHDiffPeak VIH.DIFF.Peak Voltage (DQS) | |
| VILDiffPeak VIL.DIFF.Peak Voltage (DQS) | |
| Vix_DQS_ratio DQS_t and DQS_c crossing relative to midpoint | |
| VDQSmid_to_Vcent VDQSmid offset relative to Vcent_DQ(midpoint) | |
| VIHDiff_DQS Differential Input High | |
| VILDiff_DQS Differential Input Low | |
| SRIdiff Differential Input Slew Rate (DQS) | |
| VOH(DC) DC output high measurement level (for IV curve linearity) | |
| VOM(DC) DC output mid measurement level (for IV curve linearity) | |
| VOL(DC) DC output low measurement level (for IV curve linearity) | |
| VOH(AC) AC output high measurement level (for output SR) | |
| VOL(AC) AC output low measurement level (for output SR) | |
| VOHdiff(AC) AC differential output high measurement level (for output SR) | |
| VOLdiff(AC) AC differential output low measurement level (for output SR) | |
| SRQse Single ended output slew rate | |
| SRQdiff Differential output slew rate | |
| VOH(DC) DC output high measurement level (Connectivity Test Mode) | |
| VOM(DC) DC output mid measurement level (Connectivity Test Mode) | |
| VOL(DC) DC output low measurement level (Connectivity Test Mode) | |
| VOB(DC) DC output below measurement level (Connectivity Test Mode) | |
| VOH(AC) AC output high measurement level (Connectivity Test Mode) | |
| VOL(AC) AC output below measurement level (Connectivity Test Mode) | |
| TF_output_CT Output signal Falling time (Connectivity Test Mode) | |
| TR_output_CT Output signal Rising time (Connectivity Test Mode) | |
| Absolute Specification - VDDQ = VDD | |
| Absolute Specification - VPP | |
| Speed Bin table validity condition | |
| Speed Bin table values condition | |
| tAA min (Internal read command to first data) | |
| tAA max (Internal read command to first data) | |
| tAA_DBI min (read DBI enabled) | |
| tAA_DBI max (read DBI enabled) | |
| tRCD min (ACT to internal read or write delay time) | |
| tRP min (PRE command period) | |
| tRAS min (ACT to PRE command period) | |
| tRAS max (ACT to PRE command period) | |
| tRC min (ACT to ACT or REF command period) | |
| Supported CL Settings | |
| Supported CL Settings with read DBI | |
| Supported CWL Settings | |
| CL | |
| CWL | |
| nRCD | |
| nRC | |
| nRAS | |
| nRP | |
| tCCD_S | |
| tCCD_L | |
| tWTR_S | |
| tWTR_L | |
| nRFC 2Gb | |
| nRFC 4Gb | |
| nRFC 8Gb | |
| nRFC 16Gb | |
| nFAW (x4) | |
| nFAW (x8) | |
| nFAW (x16) | |
| nRRDS (x4) | |
| nRRDS (x8) | |
| nRRDS (x16) | |
| nRRDL (x4) | |
| nRRDL (x8) | |
| nRRDL (x16) | |
| IDD measurement initialization: RON (Output Driver Impedance) | |
| IDD measurement initialization: RTT_NOM | |
| IDD measurement initialization: RTT_WR | |
| IDD measurement initialization: RTT_PARK | |
| IDD measurement initialization: Qoff | |
| Measurement condition symbol: IDD0 | |
| Measurement condition symbol: IDD0A | |
| Measurement condition symbol: IPP0 | |
| Measurement condition symbol: IDD1 | |
| Measurement condition symbol: IDD1A | |
| Measurement condition symbol: IPP1 | |
| Measurement condition symbol: IDD2N | |
| Measurement condition symbol: IDD2NA | |
| Measurement condition symbol: IPP2N | |
| Measurement condition symbol: IDD2NT | |
| Measurement condition symbol: IDDQ2NT (Optional) | |
| Measurement condition symbol: IDD2NL | |
| Measurement condition symbol: IDD2NG | |
| Measurement condition symbol: IDD2ND | |
| Measurement condition symbol: IDD2N_par | |
| Measurement condition symbol: IDD2P | |
| Measurement condition symbol: IPP2P | |
| Measurement condition symbol: IDD2Q | |
| Measurement condition symbol: IDD3N | |
| Measurement condition symbol: IDD3NA | |
| Measurement condition symbol: IPP3N | |
| Measurement condition symbol: IDD3P | |
| Measurement condition symbol: IPP3P | |
| Measurement condition symbol: IDD4R | |
| Measurement condition symbol: IDD4RA | |
| Measurement condition symbol: IDD4RB | |
| Measurement condition symbol: IPP4R | |
| Measurement condition symbol: IDDQ4R (Optional) | |
| Measurement condition symbol: IDDQ4RB (Optional) | |
| Measurement condition symbol: IDD4W | |
| Measurement condition symbol: IDD4WA | |
| Measurement condition symbol: IDD4WB | |
| Measurement condition symbol: IDD4WC | |
| Measurement condition symbol: IDD4W_par | |
| Measurement condition symbol: IPP4W | |
| Measurement condition symbol: IDD5B | |
| Measurement condition symbol: IPP5B | |
| Measurement condition symbol: IDD5F2 | |
| Measurement condition symbol: IPP5F2 | |
| Measurement condition symbol: IDD5F4 | |
| Measurement condition symbol: IPP5F4 | |
| Measurement condition symbol: IDD6N | |
| Measurement condition symbol: IPP6N | |
| Measurement condition symbol: IDD6E | |
| Measurement condition symbol: IPP6E | |
| Measurement condition symbol: IDD6R | |
| Measurement condition symbol: IPP6R | |
| Measurement condition symbol: IDD6A | |
| Measurement condition symbol: IPP6A | |
| Measurement condition symbol: IDD7 | |
| Measurement condition symbol: IPP7 | |
| Measurement condition symbol: IDD8 | |
| Measurement condition symbol: IPP8 | |
| Note 1 - Burst Length | |
| Note 2 - Output Buffer Enable | |
| Note 3 - CAL enabled | |
| Note 4 - Low Power Array Self Refresh (LP ASR) | |
| Note 5 - IDD2NG | |
| Section title | |
| IDD calculation note | |
| Module identification | |
| IDD4RB | |
| IDD4WB | |
| IPP5B | |
| Page number | |
| Module organization / part number | |
| Module length (overall) | |
| Module length (inner) | |
| Front dimension | |
| Height dimension | |
| PCB thickness | |
| Maximum component height (side) | |
| Side dimension max | |
| Notch / registering area dimension | |
| Detail E dimension | |
| Tolerance (general) | |
| Note | |
| Detail A dimension | |
| Detail dimension | |
| Component label | |
| Contact dimension (Detail of Contacts A, F) | |
| Contact dimension (Detail of Contacts E) | |
| Contact dimension (Detail of Contacts B) | |
| Pin number callout (Detail of Contacts B) | |
| Contact dimension (Detail of Contacts C) | |
| Pin number callout (Detail of Contacts C) | |
| Contact dimension (Detail of Contacts D) | |
| Keep-out note (Detail of Contacts D) | |
| Keep-out max (Detail of Contacts D) | |
| Keep-out note (Detail of Contacts D, second) | |
| Keep-out max (Detail of Contacts D, second) | |
| Detail F dimension | |
| View label | |
| DRAM die basis | |
| Disclaimer | |
| Organization | |
| Intended use | |
| Power Supply VDD | |
| Standards compliance | |
| Bank Grouping | |
| Data Strobe | |
| Burst Length | |
| On-Die Termination | |
| RoHS compliance | |
| Per DRAM Addressability | |
| Internal Vref DQ level generation | |
| DBI (Data Bus Inversion) | |
| CA parity mode | |
| Density / Organization | |
| Pin 1 (Front Side) | |
| Pin 2 (Front Side) | |
| Pin 3 (Front Side) | |
| Pin 4 (Front Side) | |
| Pin 5 (Front Side) | |
| Pin 6 (Front Side) | |
| Pin 7 (Front Side) | |
| Pin 8 (Front Side) | |
| Pin 9 (Front Side) | |
| Pin 10 (Front Side) | |
| Pin 11 (Front Side) | |
| Pin 12 (Front Side) | |
| Pin 13 (Front Side) | |
| Pin 14 (Front Side) | |
| Pin 15 (Front Side) | |
| Pin 16 (Front Side) | |
| Pin 17 (Front Side) | |
| Pin 18 (Front Side) | |
| Pin 19 (Front Side) | |
| Pin 20 (Front Side) | |
| Pin 21 (Front Side) | |
| Pin 22 (Front Side) | |
| Pin 23 (Front Side) | |
| Pin 24 (Front Side) | |
| Pin 25 (Front Side) | |
| Pin 26 (Front Side) | |
| Pin 27 (Front Side) | |
| Pin 28 (Front Side) | |
| Pin 29 (Front Side) | |
| Pin 30 (Front Side) | |
| Pin 31 (Front Side) | |
| Pin 32 (Front Side) | |
| Pin 33 (Front Side) | |
| Pin 34 (Front Side) | |
| Pin 35 (Front Side) | |
| Pin 36 (Front Side) | |
| Pin 145 (Back Side) | |
| Pin 146 (Back Side) | |
| Pin 147 (Back Side) | |
| Pin 148 (Back Side) | |
| Pin 149 (Back Side) | |
| Pin 150 (Back Side) | |
| Pin 151 (Back Side) | |
| Pin 152 (Back Side) | |
| Pin 153 (Back Side) | |
| Pin 154 (Back Side) | |
| Pin 155 (Back Side) | |
| Pin 156 (Back Side) | |
| Pin 157 (Back Side) | |
| Pin 158 (Back Side) | |
| Pin 159 (Back Side) | |
| Pin 160 (Back Side) | |
| Pin 161 (Back Side) | |
| Pin 162 (Back Side) | |
| Pin 163 (Back Side) | |
| Pin 164 (Back Side) | |
| Pin 165 (Back Side) | |
| Pin 166 (Back Side) | |
| Pin 167 (Back Side) | |
| Pin 168 (Back Side) | |
| Pin 169 (Back Side) | |
| Pin 170 (Back Side) | |
| Pin 171 (Back Side) | |
| Pin 172 (Back Side) | |
| Pin 173 (Back Side) | |
| Pin 174 (Back Side) | |
| Pin 175 (Back Side) | |
| Pin 176 (Back Side) | |
| Pin 177 (Back Side) | |
| Pin 178 (Back Side) | |
| Pin 179 (Back Side) | |
| Pin 180 (Back Side) | |
| Pin 74 (Front Side) | |
| Pin 75 (Front Side) | |
| Pin 76 (Front Side) | |
| Pin 77 (Front Side) | |
| Pin 78 (Front Side) | |
| Pin 79 (Front Side) | |
| Pin 80 (Front Side) | |
| Pin 81 (Front Side) | |
| Pin 82 (Front Side) | |
| Pin 83 (Front Side) | |
| Pin 84 (Front Side) | |
| Pin 85 (Front Side) | |
| Pin 86 (Front Side) | |
| Pin 87 (Front Side) | |
| Pin 88 (Front Side) | |
| Pin 89 (Front Side) | |
| Pin 90 (Front Side) | |
| Pin 91 (Front Side) | |
| Pin 92 (Front Side) | |
| Pin 93 (Front Side) | |
| Pin 94 (Front Side) | |
| Pin 95 (Front Side) | |
| Pin 96 (Front Side) | |
| Pin 97 (Front Side) | |
| Pin 98 (Front Side) | |
| Pin 99 (Front Side) | |
| Pin 100 (Front Side) | |
| Pin 101 (Front Side) | |
| Pin 102 (Front Side) | |
| Pin 103 (Front Side) | |
| Pin 104 (Front Side) | |
| Pin 105 (Front Side) | |
| Pin 106 (Front Side) | |
| Pin 107 (Front Side) | |
| Pin 218 (Back Side) | |
| Pin 219 (Back Side) | |
| Pin 220 (Back Side) | |
| Pin 221 (Back Side) | |
| Pin 222 (Back Side) | |
| Pin 223 (Back Side) | |
| Pin 224 (Back Side) | |
| Pin 225 (Back Side) | |
| Pin 226 (Back Side) | |
| Pin 227 (Back Side) | |
| Pin 228 (Back Side) | |
| Pin 229 (Back Side) | |
| Pin 230 (Back Side) | |
| Pin 231 (Back Side) | |
| Pin 232 (Back Side) | |
| Pin 233 (Back Side) | |
| Pin 234 (Back Side) | |
| Pin 235 (Back Side) | |
| Pin 236 (Back Side) | |
| Pin 237 (Back Side) | |
| Pin 238 (Back Side) | |
| Pin 239 (Back Side) | |
| Pin 240 (Back Side) | |
| Pin 241 (Back Side) | |
| Pin 242 (Back Side) | |
| Pin 243 (Back Side) | |
| Pin 244 (Back Side) | |
| Pin 245 (Back Side) | |
| Pin 246 (Back Side) | |
| Pin 247 (Back Side) | |
| Pin 248 (Back Side) | |
| Pin 249 (Back Side) | |
| Pin 250 (Back Side) | |
| Pin 251 (Back Side) | |
| Pin 37 (Front Side) | |
| Pin 38 (Front Side) | |
| Pin 39 (Front Side) | |
| Pin 40 (Front Side) | |
| Pin 41 (Front Side) | |
| Pin 42 (Front Side) | |
| Pin 43 (Front Side) | |
| Pin 44 (Front Side) | |
| Pin 45 (Front Side) | |
| Pin 46 (Front Side) | |
| Pin 47 (Front Side) | |
| Pin 48 (Front Side) | |
| Pin 49 (Front Side) | |
| Pin 50 (Front Side) | |
| Pin 51 (Front Side) | |
| Pin 52 (Front Side) | |
| Pin 53 (Front Side) | |
| Pin 54 (Front Side) | |
| Pin 55 (Front Side) | |
| Pin 56 (Front Side) | |
| Pin 57 (Front Side) | |
| Pin 58 (Front Side) | |
| Pin 59 (Front Side) | |
| Pin 60 (Front Side) | |
| Pin 61 (Front Side) | |
| Pin 62 (Front Side) | |
| Pin 63 (Front Side) | |
| Pin 64 (Front Side) | |
| Pin 65 (Front Side) | |
| Pin 66 (Front Side) | |
| Pin 67 (Front Side) | |
| Pin 68 (Front Side) | |
| Pin 69 (Front Side) | |
| Pin 70 (Front Side) | |
| Pin 71 (Front Side) | |
| Pin 72 (Front Side) | |
| Pin 73 (Front Side) | |
| Pin 181 (Back Side) | |
| Pin 182 (Back Side) | |
| Pin 183 (Back Side) | |
| Pin 184 (Back Side) | |
| Pin 185 (Back Side) | |
| Pin 186 (Back Side) | |
| Pin 187 (Back Side) | |
| Pin 188 (Back Side) | |
| Pin 189 (Back Side) | |
| Pin 190 (Back Side) | |
| Pin 191 (Back Side) | |
| Pin 192 (Back Side) | |
| Pin 193 (Back Side) | |
| Pin 194 (Back Side) | |
| Pin 195 (Back Side) | |
| Pin 196 (Back Side) | |
| Pin 197 (Back Side) | |
| Pin 198 (Back Side) | |
| Pin 199 (Back Side) | |
| Pin 200 (Back Side) | |
| Pin 201 (Back Side) | |
| Pin 202 (Back Side) | |
| Pin 203 (Back Side) | |
| Pin 204 (Back Side) | |
| Pin 205 (Back Side) | |
| Pin 206 (Back Side) | |
| Pin 207 (Back Side) | |
| Pin 208 (Back Side) | |
| Pin 209 (Back Side) | |
| Pin 210 (Back Side) | |
| Pin 211 (Back Side) | |
| Pin 212 (Back Side) | |
| Pin 213 (Back Side) | |
| Pin 214 (Back Side) | |
| Pin 215 (Back Side) | |
| Pin 216 (Back Side) | |
| Pin 217 (Back Side) | |
| Pin 108 (Front Side) | |
| Pin 109 (Front Side) | |
| Pin 110 (Front Side) | |
| Pin 111 (Front Side) | |
| Pin 112 (Front Side) | |
| Pin 113 (Front Side) | |
| Pin 114 (Front Side) | |
| Pin 115 (Front Side) | |
| Pin 116 (Front Side) | |
| Pin 117 (Front Side) | |
| Pin 118 (Front Side) | |
| Pin 119 (Front Side) | |
| Pin 120 (Front Side) | |
| Pin 121 (Front Side) | |
| Pin 122 (Front Side) | |
| Pin 123 (Front Side) | |
| Pin 124 (Front Side) | |
| Pin 125 (Front Side) | |
| Pin 126 (Front Side) | |
| Pin 127 (Front Side) | |
| Pin 128 (Front Side) | |
| Pin 129 (Front Side) | |
| Pin 130 (Front Side) | |
| Pin 131 (Front Side) | |
| Pin 132 (Front Side) | |
| Pin 133 (Front Side) | |
| Pin 134 (Front Side) | |
| Pin 135 (Front Side) | |
| Pin 136 (Front Side) | |
| Pin 137 (Front Side) | |
| Pin 138 (Front Side) | |
| Pin 139 (Front Side) | |
| Pin 140 (Front Side) | |
| Pin 141 (Front Side) | |
| Pin 142 (Front Side) | |
| Pin 143 (Front Side) | |
| Pin 144 (Front Side) | |
| Pin 252 (Back Side) | |
| Pin 253 (Back Side) | |
| Pin 254 (Back Side) | |
| Pin 255 (Back Side) | |
| Pin 256 (Back Side) | |
| Pin 257 (Back Side) | |
| Pin 258 (Back Side) | |
| Pin 259 (Back Side) | |
| Pin 260 (Back Side) | |
| Pin 261 (Back Side) | |
| Pin 262 (Back Side) | |
| Pin 263 (Back Side) | |
| Pin 264 (Back Side) | |
| Pin 265 (Back Side) | |
| Pin 266 (Back Side) | |
| Pin 267 (Back Side) | |
| Pin 268 (Back Side) | |
| Pin 269 (Back Side) | |
| Pin 270 (Back Side) | |
| Pin 271 (Back Side) | |
| Pin 272 (Back Side) | |
| Pin 273 (Back Side) | |
| Pin 274 (Back Side) | |
| Pin 275 (Back Side) | |
| Pin 276 (Back Side) | |
| Pin 277 (Back Side) | |
| Pin 278 (Back Side) | |
| Pin 279 (Back Side) | |
| Pin 280 (Back Side) | |
| Pin 281 (Back Side) | |
| Pin 282 (Back Side) | |
| Pin 283 (Back Side) | |
| Pin 284 (Back Side) | |
| Pin 285 (Back Side) | |
| Pin 286 (Back Side) | |
| Pin 287 (Back Side) | |
| Pin 288 (Back Side) | |
| Key (notch) position | |
| VDD Absolute Max | |
| VDDQ Absolute Max | |
| VPP Absolute Max | |
| VIN, VOUT Absolute Max | |
| TSTG Storage Temperature | |
| TOPER Normal Operating Temperature Range | |
| TOPER Extended Temperature Range | |
| VDDQ Supply Voltage for Output | |
| VPP Supply Voltage for DRAM Activating | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate > 4.0 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 4.0 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 3.0 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 2.0 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 1.8 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 1.6 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 1.4 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 1.2 | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV, Slew Rate 1.0 | |
| VDDQ = VDD | |
| DLL condition | |
| Geardown validity | |
| tAA (min) | |
| tAA (max) | |
| tAA_DBI (min) | |
| tAA_DBI (max) | |
| tRCD (min) | |
| tRCD (max) | |
| tRP (min) | |
| tRP (max) | |
| tRAS (min) | |
| tRAS (max) | |
| tRC (min) | |
| tRC (max) | |
| nFAW x4 | |
| nFAW x8 | |
| nFAW x16 | |
| nRRDS x4 | |
| nRRDS x8 | |
| nRRDS x16 | |
| nRRDL x4 | |
| nRRDL x8 | |
| nRRDL x16 | |
| Module density / configuration | |
| Revision date | |
| Module configuration | |
| Module length (Front, overall) | |
| Module length (Front, inner) | |
| Notch/feature height | |
| Dimension | |
| Module height (Back) | |
| Module dimension (Back) | |
| PCB thickness tolerance | |
| Maximum thickness (Side) | |
| General tolerance | |
| Drawing note | |
| Pin callout | |
| Contact dimension | |
| Keep-out area note | |
| Keep-out dimension (max) | |
| DRAM die base | |
| Compliance | |
| Internal Vref DQ | |
| DBI | |
| VDD core power supply | |
| VPP SDRAM activating power supply | |
| VTT termination power supply | |
| 12V supply usage | |
| VDDSPD supply | |
| VREFCA reference voltage | |
| VDD for PC4 | |
| Data bus width | |
| ECC check bits | |
| Functional block diagram title | |
| Module type (register present) | |
| CK0_t/CK0_c termination resistor | |
| CK1_t/CK1_c termination resistor | |
| Default resistor value (page1, command/address/control) | |
| Default resistor value (page2/3, data bus) | |
| ZQ resistor value | |
| DRAM TEN pin connection | |
| VDDSPD connection | |
| VREFCA routing | |
| Net Structure reference | |
| SDRAM device count (data, D0-D35) | |
| DQS / data byte mapping (rank A, page2 left column) | |
| DQS / data byte mapping (rank, page2 right column) | |
| DQS / data byte mapping (page3 left column) | |
| DQS / data byte mapping (page3 right column) | |
| SPD / thermal sensor features | |
| Register (RCD) ZQCAL resistor | |
| Register (RCD) signals | |
| Module power/reference rails | |
| Module package layout (front/back) | |
| Command/address/control bus signals | |
| VIN, VOUT | |
| Extended Temperature Range | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate > 4.0 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 4.0 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 3.0 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 2.0 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 1.8 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 1.6 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 1.4 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 1.2 V/ns) | |
| tDVAC @ |VIH/Ldiff(AC)|=200mV (Slew Rate 1.0 V/ns) | |
| Maximum peak amplitude above VDD Absolute Max allowed for overshoot area | |
| Delta value between VDD Absolute Max and VDD Max allowed for overshoot area | |
| Maximum peak amplitude allowed for undershoot area | |
| Maximum overshoot area per 1tCK Above Absolute Max | |
| Maximum overshoot area per 1tCK Between Absolute Max | |
| Maximum undershoot area per 1tCK Below VSS | |
| Clock: Maximum peak amplitude above VDD Absolute Max allowed for overshoot area | |
| Clock: Delta value between VDD Absolute Max and VDD Max allowed for overshoot area | |
| Clock: Maximum peak amplitude allowed for undershoot area | |
| Clock: Maximum overshoot area per 1UI Above Absolute Max | |
| Clock: Maximum overshoot area per 1UI Between Absolute Max | |
| Clock: Maximum undershoot area per 1UI Below VSS | |
| Data/Strobe/Mask: Maximum peak amplitude above Max absolute level of Vin,Vout | |
| Data/Strobe/Mask: Overshoot area Between Max Absolute level of Vin,Vout and VDDQ Max | |
| Data/Strobe/Mask: Undershoot area Between Min absolute level of Vin,Vout and VDDQ Max | |
| Data/Strobe/Mask: Maximum peak amplitude below Min absolute level of Vin,Vout | |
| Data/Strobe/Mask: Maximum overshoot area per 1UI Above Max absolute level of Vin,Vout | |
| Data/Strobe/Mask: Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and VDDQ Max | |
| Data/Strobe/Mask: Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and VSSQ | |
| Data/Strobe/Mask: Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout | |
| AC Input High Voltage VIH(AC)_RESET | |
| DC Input High Voltage VIH(DC)_RESET | |
| DC Input Low Voltage VIL(DC)_RESET | |
| AC Input Low Voltage VIL(AC)_RESET | |
| Rising time TR_RESET | |
| RESET pulse width tPW_RESET | |
| VIHDiffPeak VIH.DIFF.Peak Voltage | |
| VILDiffPeak VIL.DIFF.Peak Voltage | |
| SRIdiff Differential Input Slew Rate | |
| VOH(DC) DC output high measurement level | |
| VOM(DC) DC output mid measurement level | |
| VOL(DC) DC output low measurement level | |
| VOH(AC) AC output high measurement level | |
| VOL(AC) AC output low measurement level | |
| VOHdiff(AC) AC differential output high measurement level | |
| VOLdiff(AC) AC differential output low measurement level | |
| CT Mode VOH(DC) DC output high measurement level | |
| CT Mode VOM(DC) DC output mid measurement level | |
| CT Mode VOL(DC) DC output low measurement level | |
| CT Mode VOB(DC) DC output below measurement level | |
| CT Mode VOH(AC) AC output high measurement level | |
| CT Mode VOL(AC) AC output below measurement level | |
| CT Mode TF_output_CT Output signal Falling time | |
| CT Mode TR_output_CT Output signal Rising time | |
| tAA (Internal read command to first data) min | |
| tAA max | |
| tAA_DBI min | |
| tAA_DBI max | |
| tRCD min | |
| tRP min | |
| tRAS min | |
| tRAS max | |
| tRC min | |
| tAA min | |
| Speed Bin Table DLL condition | |
| Geardown Mode condition | |
| IDD note | |
| Drawing title | |
| Overall module width (Front, outer) | |
| Module width (Front) | |
| Contact field width (left, Front) | |
| Contact field width (right, Front) | |
| Module height (Front) | |
| Height to notch / lower feature (Front) | |
| Side thickness | |
| Side thickness (max) | |
| Tolerance note value | |
| Note 1 (tolerance) | |
| Note 2 (disclaimer) | |
| Corner radius (Detail A area) | |
| Pin callout (Detail A) | |
| Component label (Front) | |
| Detail B/D dimension | |
| Pin callout (Detail of Contacts B) | |
| Pin callout (Detail of Contacts C) | |
| Keep-out dimension (Detail of Contacts D) | |
| Keep-out note (Detail of Contacts E) | |
| Keep-out dimension (Detail of Contacts E) | |
| Interface | |
| Module density / organization | |
| VDD (Absolute Max) - Voltage on VDD pin relative to Vss | |
| VDDQ (Absolute Max) - Voltage on VDDQ pin relative to Vss | |
| VPP (Absolute Max) - Voltage on VPP pin relative to Vss | |
| VIN, VOUT (Absolute Max) - Voltage on any pin except VREFCA relative to Vss | |
| VDD - Supply Voltage (Min) | |
| VDD - Supply Voltage (Typ) | |
| VDD - Supply Voltage (Max) | |
| VDDQ - Supply Voltage for Output (Min) | |
| VDDQ - Supply Voltage for Output (Typ) | |
| VDDQ - Supply Voltage for Output (Max) | |
| VPP - Supply Voltage for DRAM Activating (Min) | |
| VPP - Supply Voltage for DRAM Activating (Typ) | |
| VPP - Supply Voltage for DRAM Activating (Max) | |
| VIH.CA(DC75) DC input logic high (Min) - DDR4-1600/1866/2133/2400 | |
| VIH.CA(DC75) DC input logic high (Min) - DDR4-2666/2933/3200 | |
| VIL.CA(DC75) DC input logic low (Max) - DDR4-1600/1866/2133/2400 | |
| VIL.CA(DC75) DC input logic low (Max) - DDR4-2666/2933/3200 | |
| VIH.CA(AC100) AC input logic high (Min) - DDR4-1600/1866/2133/2400 | |
| VIH.CA(AC100) AC input logic high (Min) - DDR4-2666/2933/3200 | |
| VIL.CA(AC100) AC input logic low (Max) - DDR4-1600/1866/2133/2400 | |
| VIL.CA(AC100) AC input logic low (Max) - DDR4-2666/2933/3200 | |
| VREFCA(DC) Reference Voltage for ADD,CMD inputs (Min) | |
| VREFCA(DC) Reference Voltage for ADD,CMD inputs (Max) | |
| VIHdiff differential input high (Min) - DDR4-1600,1866,2133 | |
| VIHdiff differential input high (Min) - DDR4-2400 | |
| VIHdiff differential input high (Min) - DDR4-2666 | |
| VIHdiff differential input high (Min) - DDR4-2933 | |
| VIHdiff differential input high (Min) - DDR4-3200 | |
| VILdiff differential input low (Max) - DDR4-1600,1866,2133 | |
| VILdiff differential input low (Max) - DDR4-2400 | |
| VILdiff differential input low (Max) - DDR4-3200 | |
| tDVAC for CK_t-CK_c @ |VIH/Ldiff(AC)|=200mV, Slew Rate > 4.0 V/ns (min) | |
| tDVAC for CK_t-CK_c @ |VIH/Ldiff(AC)|=200mV, Slew Rate 1.0 V/ns (min) | |
| VSEH Single-ended high-level for CK_t,CK_c - DDR4-1600/1866/2133 | |
| VSEH Single-ended high-level for CK_t,CK_c - DDR4-2400 | |
| VSEH Single-ended high-level for CK_t,CK_c - DDR4-2933/3200 | |
| VSEL Single-ended low-level for CK_t,CK_c - DDR4-1600/1866/2133 | |
| VSEL Single-ended low-level for CK_t,CK_c - DDR4-2933/3200 | |
| ADD/CMD/CTRL Max peak amplitude above VDD Absolute Max allowed for overshoot area | |
| ADD/CMD/CTRL Delta value between VDD Absolute Max and VDD Max allowed for overshoot area | |
| ADD/CMD/CTRL Max peak amplitude allowed for undershoot area | |
| ADD/CMD/CTRL Max overshoot area per 1tCK Above Absolute Max - DDR4-1600 | |
| ADD/CMD/CTRL Max overshoot area per 1tCK Above Absolute Max - DDR4-3200 | |
| ADD/CMD/CTRL Max overshoot area per 1tCK Between Absolute Max - DDR4-1600 | |
| ADD/CMD/CTRL Max undershoot area per 1tCK Below VSS - DDR4-1600 | |
| Clock Max peak amplitude above VDD Absolute Max allowed for overshoot area | |
| Clock Max overshoot area per 1UI Above Absolute Max - DDR4-1600 | |
| Clock Max overshoot area per 1UI Above Absolute Max - DDR4-3200 | |
| Clock Max overshoot area per 1UI Between Absolute Max - DDR4-1600 | |
| Clock Max undershoot area per 1UI Below VSS - DDR4-1600 | |
| Data/Strobe/Mask Max peak amplitude above Max absolute level of Vin,Vout | |
| Data/Strobe/Mask Overshoot area Between Max Absolute level of Vin,Vout and VDDQ Max | |
| Data/Strobe/Mask Undershoot area Between Min absolute level of Vin,Vout and VDDQ Max | |
| Data/Strobe/Mask Max peak amplitude below Min absolute level of Vin,Vout | |
| Data/Strobe/Mask Max overshoot area per 1UI Above Max absolute level - DDR4-1600 | |
| Data/Strobe/Mask Max overshoot area per 1UI Between Max absolute level and VDDQ Max - DDR4-1600 | |
| VIX(CK) Differential Input Cross Point Voltage relative to VDD/2 (min) - DDR4-1600/1866/2133 | |
| VIX(CK) Differential Input Cross Point Voltage relative to VDD/2 (max) - DDR4-1600/1866/2133 | |
| VIX(CK) Differential Input Cross Point Voltage relative to VDD/2 (min) - DDR4-2400/2666/2933/3200 | |
| VIX(CK) Differential Input Cross Point Voltage relative to VDD/2 (max) - DDR4-2400/2666/2933/3200 | |
| VIH(AC)_RESET AC Input High Voltage (Min) | |
| VIH(AC)_RESET AC Input High Voltage (Max) | |
| VIH(DC)_RESET DC Input High Voltage (Min) | |
| VIL(DC)_RESET DC Input Low Voltage (Max) | |
| VIL(AC)_RESET AC Input Low Voltage (Max) | |
| TR_RESET Rising time (Max) | |
| tPW_RESET RESET pulse width (Min) | |
| VIH.DIFF.Peak Voltage (DQS) (Min) - DDR4-1600,1866,2133 | |
| VIH.DIFF.Peak Voltage (DQS) (Min) - DDR4-2400 | |
| VIH.DIFF.Peak Voltage (DQS) (Min) - DDR4-2666,2933,3200 | |
| VIL.DIFF.Peak Voltage (DQS) (Max) - DDR4-1600,1866,2133 | |
| VIL.DIFF.Peak Voltage (DQS) (Max) - DDR4-2666,2933,3200 | |
| Vix_DQS_ratio DQS crossing relative to midpoint (Max) | |
| VDQSmid_to_Vcent VDQSmid offset relative to Vcent_DQ midpoint (Max) | |
| VIHDiff_DQS Differential Input High (Min) - DDR4-1600,1866,2133 | |
| VIHDiff_DQS Differential Input High (Min) - DDR4-2400 | |
| VIHDiff_DQS Differential Input High (Min) - DDR4-2666 | |
| VIHDiff_DQS Differential Input High (Min) - DDR4-2933 | |
| VIHDiff_DQS Differential Input High (Min) - DDR4-3200 | |
| VILDiff_DQS Differential Input Low (Max) - DDR4-1600,1866,2133 | |
| VILDiff_DQS Differential Input Low (Max) - DDR4-3200 | |
| SRIdiff Differential Input Slew Rate (Min) - DDR4-1600,1866,2133 | |
| SRIdiff Differential Input Slew Rate (Min) - DDR4-2666/2933/3200 | |
| SRIdiff Differential Input Slew Rate (Max) | |
| SRQse Single ended output slew rate (Min) - all speed bins | |
| SRQse Single ended output slew rate (Max) - all speed bins | |
| SRQdiff Differential output slew rate (Min) - all speed bins | |
| SRQdiff Differential output slew rate (Max) - all speed bins | |
| Connectivity Test Mode VOH(DC) DC output high measurement level | |
| Connectivity Test Mode VOB(DC) DC output below measurement level | |
| Connectivity Test Mode VOH(AC) AC output high measurement level | |
| Connectivity Test Mode TF_output_CT Output signal Falling time (Max) | |
| Connectivity Test Mode TR_output_CT Output signal Rising time (Max) | |
| Absolute Specification VDDQ = VDD | |
| Absolute Specification VPP | |
| Speed bin table validity condition | |
| IDD measurement init RON | |
| IDD measurement init RTT_NOM | |
| IDD measurement init RTT_WR | |
| IDD measurement init RTT_PARK | |
| IDD measurement DIMM IDDQ note | |
| Module density | |
| IDD Specification note | |
| Drawing subtitle | |
| Module overall length (outer) | |
| PCB edge to first contact / component offset | |
| Component / feature dimension | |
| Front contact span dimension | |
| Module thickness (Detail E) | |
| Notch / feature offset | |
| Module height dimension | |
| PCB thickness (Side) | |
| Module max thickness (Side) | |
| Tolerance value | |
| Diagram reference note | |
| Feature dimension (Detail A) | |
| Contact pin number | |
| Feature dimension | |
| Contact width (Detail of Contacts A, F) | |
| Contact pitch (Detail of Contacts A, F) | |
| Contact pin number (Detail of Contacts B) | |
| Contact pin number (Detail of Contacts C) | |
| Keep-out area note (Detail of Contacts D) | |
| Contact width (Detail of Contacts D) | |
| Contact pitch (Detail of Contacts D) | |
| Keep-out area note (Detail D second instance) | |
| Keep-out dimension | |
| Feature dimension (Detail F) | |
| Based On | |
| Document Date | |
| module_organization | |
| rank | |
| sdram_width | |
| ck0_termination_resistor | |
| ck1_termination_resistor | |
| default_resistor_value | |
| data_bus_resistor_value | |
| zq_resistor_value | |
| Absolute Maximum: Voltage on VDD pin relative to Vss | |
| Absolute Maximum: Voltage on VDDQ pin relative to Vss | |
| Absolute Maximum: Voltage on VPP pin relative to Vss | |
| Absolute Maximum: Voltage on any pin except VREFCA relative to Vss (VIN, VOUT) | |
| Storage Temperature (TSTG) | |
| Normal Operating Temperature Range (TOPER) | |
| Extended Temperature Range (TOPER) | |
| Recommended DC: VDD Supply Voltage Min | |
| Recommended DC: VDD Supply Voltage Typ | |
| Recommended DC: VDD Supply Voltage Max | |
| Recommended DC: VDDQ Supply Voltage for Output Min | |
| Recommended DC: VDDQ Supply Voltage for Output Typ | |
| Recommended DC: VDDQ Supply Voltage for Output Max | |
| Recommended DC: VPP Supply Voltage for DRAM Activating Min | |
| Recommended DC: VPP Supply Voltage for DRAM Activating Typ | |
| Recommended DC: VPP Supply Voltage for DRAM Activating Max | |
| VREFCA(DC) Reference Voltage for ADD, CMD inputs Min (DDR4-1600/1866/2133/2400) | |
| VREFCA(DC) Reference Voltage for ADD, CMD inputs Max (DDR4-1600/1866/2133/2400) | |
| VIH.CA(DC75) DC input logic high (DDR4-1600/1866/2133/2400) | |
| VIH.CA(DC75) DC input logic high (DDR4-2666/2933/3200) | |
| VIHdiff differential input high (DDR4-1600,1866,2133) Min | |
| VIHdiff differential input high (DDR4-2400) Min | |
| VIHdiff differential input high (DDR4-2933) Min | |
| VIHdiff differential input high (DDR4-3200) Min | |
| VILdiff differential input low (DDR4-1600,1866,2133) Max | |
| tDVAC for CK_t-CK_c @ |VIH/Ldiff(AC)|=200mV, slew rate >4.0 V/ns Min | |
| tDVAC for CK_t-CK_c @ |VIH/Ldiff(AC)|=200mV, slew rate <1.0 V/ns Min | |
| VSEH single-ended high-level for CK_t,CK_c (DDR4-1600/1866/2133) | |
| VSEH single-ended high-level for CK_t,CK_c (DDR4-3200) | |
| ADD/CMD/Control overshoot: Maximum peak amplitude above VDD Absolute Max | |
| ADD/CMD/Control: Max overshoot area per 1tCK above Absolute Max (DDR4-1600) | |
| ADD/CMD/Control: Max undershoot area per 1tCK below VSS (DDR4-1600) | |
| Clock overshoot: Max overshoot area per 1UI above Absolute Max (DDR4-1600) | |
| Data/Strobe/Mask: Max peak amplitude above Max absolute level of Vin,Vout | |
| RESET_n AC Input High Voltage VIH(AC)_RESET Min | |
| RESET_n DC Input High Voltage VIH(DC)_RESET Min | |
| RESET_n DC Input Low Voltage VIL(DC)_RESET Max | |
| RESET_n AC Input Low Voltage VIL(AC)_RESET Max | |
| RESET_n Rising time TR_RESET Max | |
| RESET_n pulse width tPW_RESET Min | |
| VIHDiffPeak VIH.DIFF.Peak Voltage for DQS (DDR4-1600,1866,2133) Min | |
| VIHDiffPeak VIH.DIFF.Peak Voltage for DQS (DDR4-2400) Min | |
| VIHDiffPeak VIH.DIFF.Peak Voltage for DQS (DDR4-2666,2933,3200) Min | |
| Vix_DQS_ratio DQS crossing relative to midpoint Max | |
| VIHDiff_DQS Differential Input High (DDR4-1600,1866,2133) Min | |
| VIHDiff_DQS Differential Input High (DDR4-2400) Min | |
| VIHDiff_DQS Differential Input High (DDR4-2933) Min | |
| VIHDiff_DQS Differential Input High (DDR4-3200) Min | |
| SRIdiff Differential Input Slew Rate for DQS (DDR4-1600,1866,2133) Min | |
| SRIdiff Differential Input Slew Rate for DQS (DDR4-2666/2933/3200) Min | |
| SRIdiff Differential Input Slew Rate for DQS Max | |
| Single-ended output slew rate SRQse Min | |
| Single-ended output slew rate SRQse Max | |
| Differential output slew rate SRQdiff Min | |
| Differential output slew rate SRQdiff Max | |
| Connectivity Test Mode: Output signal Falling time TF_output_CT Max | |
| Connectivity Test Mode: Output signal Rising time TR_output_CT Max | |
| Spec section note | |
| tAA (Internal read command to first data), min | |
| tAA, max | |
| tAA_DBI (read command to first data with read DBI enabled), min | |
| tAA_DBI, max | |
| tRCD (ACT to internal read or write delay time), min | |
| tRP (PRE command period), min | |
| tRAS (ACT to PRE command period), min | |
| tRAS, max | |
| tRC (ACT to ACT or REF command period), min | |
| tCK(AVG), CL=11 / CWL=9, min | |
| tAA, min | |
| tRCD, min | |
| tRP, min | |
| tRAS, min | |
| tRC, min | |
| tAA_DBI, min | |
| Absolute specification VDDQ = VDD | |
| Absolute specification VPP | |
| tCK (Table 1 timing) | |
| CL (Table 1) | |
| CWL (Table 1) | |
| nRCD (Table 1) | |
| nRC (Table 1) | |
| nRAS (Table 1) | |
| nRP (Table 1) | |
| nFAW x4 (Table 1) | |
| nFAW x8 (Table 1) | |
| nFAW x16 (Table 1) | |
| nRRDS x4 (Table 1) | |
| nRRDS x8 (Table 1) | |
| nRRDS x16 (Table 1) | |
| nRRDL x4 (Table 1) | |
| nRRDL x8 (Table 1) | |
| nRRDL x16 (Table 1) | |
| tCCD_S (Table 1) | |
| tCCD_L (Table 1) | |
| tWTR_S (Table 1) | |
| tWTR_L (Table 1) | |
| nRFC 2Gb (Table 1) | |
| nRFC 4Gb (Table 1) | |
| nRFC 8Gb (Table 1) | |
| nRFC 16Gb (Table 1) | |
| IDD measurement setup RON | |
| IDD measurement setup RTT_NOM | |
| IDD measurement setup RTT_WR | |
| IDD/IPP/IDDQ measurement conditions & loop patterns | |
| IDD6N Self Refresh temperature range (Normal) | |
| IDD6E Self Refresh temperature range (Extended) | |
| IDD6R Self Refresh temperature range (Reduced) | |
| IDD6A Auto Self-Refresh temperature range | |
| Module type / density | |
| Dimension units | |
| Module overall length | |
| Module height (inner) | |
| Contact field length (left) | |
| Contact field length (right) | |
| Edge / notch offset dimension | |
| Edge dimension | |
| Maximum component height | |
| Back view dimension | |
| Dimensional tolerance (unstated) | |
| Note 2 | |
| Edge radius | |
| Notch / key dimension | |
| Contact pin reference | |
| Component callout | |
| Contact detail dimension | |
| Contact pad height | |
| Contact pad thickness | |
| Non-metallized keep out area | |
| Document revision / date |
