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HMA81GR7DJR8N (SK hynix)
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| Speed Mt S | 1600 |
|---|---|
| Memory Class | rdimm |
| Die Density Gb | 8 |
| Registered | true |
| Pin Count | 288 |
| Capacity Gb | 8 |
| Voltage Vdd V | 1.2 |
| Memory Generation | ddr4 |
| Ecc | Supports ECC error correction and detection |
| Product Name | DDR4 SDRAM RDIMM Based on 8Gb D-die |
| Bank Address In A Bg | |
| Bg Address | |
| Ca Parity | |
| Column Address | |
| Component Composition | |
| Data Transfer Rates | |
| Die Type | |
| Document Revision |
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| Idd0 |
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| Idd0a |
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| Idd1 |
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| Idd1a |
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| Idd2n |
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| Idd2na |
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| Idd2nd |
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| Idd2ng |
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| Idd2nl |
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| Idd2np |
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| Idd2nt |
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| Idd2p |
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| Idd2q |
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| Idd3n |
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| Idd3na |
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| Idd3p |
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| Idd4r |
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| Idd4ra |
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| Idd4w |
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| Idd4wa |
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| Idd4wc |
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| Idd4wp |
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| Idd5b |
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| Idd5f2 |
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| Idd5f4 |
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| Idd6a |
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| Idd6e |
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| Idd6n |
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| Idd6r |
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| Idd7 |
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| Idd8 |
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| Internal Banks |
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| Ipp0 |
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| Ipp1 |
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| Ipp2n |
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| Ipp2p |
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| Ipp3n |
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| Ipp3p |
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| Ipp4r |
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| Ipp4w |
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| Ipp5f2 |
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| Ipp5f4 |
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| Ipp6a |
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| Ipp6e |
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| Ipp6n |
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| Ipp6r |
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| Ipp7 |
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| Ipp8 |
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| Module Description |
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| Of Bank Groups |
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| Of Ranks |
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| Pre Fetch |
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| Product Type |
|---|
| Row Address |
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| Temperature Sensor |
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| Vddq |
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| Vddspd |
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| Voltage Vpp V |
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| Write Crc |
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| Operating temp max (°C) | 85 |
|---|---|
| Operating temp min (°C) | 0 |
| SKU | HMA81GR7DJR8N |
|---|
| Revision | |
|---|---|
| Revision Date | |
| Notice | |
| Organization | |
| Intended use | |
| Power Supply VDD | |
| DDR4 SDRAM datasheet compliance | |
| Bank Grouping | |
| Data Strobe | |
| Burst Length | |
| On-Die Termination | |
| RoHS | |
| Per DRAM Addressability | |
| Internal Vref DQ | |
| DBI | |
| Address Table column | |
| Page size | |
| Downbinning support | |
| Timing DDR4-1600 (-PB): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Timing DDR4-1866 (-RD): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Timing DDR4-2133 (-TF): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Timing DDR4-2400 (-UH): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Timing DDR4-2666 (-VK): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Timing DDR4-2933 (-WM): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Timing DDR4-3200 (-XN): tCK / CL / tRCD / tRP / tRAS / tRC / CL-tRCD-tRP | |
| Supply voltage (VDD) | |
| PC4 supply voltage note (VDD) | |
| VPP SDRAM activating power supply | |
| VTT termination supply | |
| 12V supply usage | |
| VDD Absolute Maximum (Voltage on VDD pin relative to Vss) | |
| VDDQ Absolute Maximum (Voltage on VDDQ pin relative to Vss) | |
| VPP Absolute Maximum (Voltage on VPP pin relative to Vss) | |
| VIN, VOUT Absolute Maximum (Voltage on any pin except VREFCA relative to Vss) | |
| TSTG Storage Temperature | |
| TOPER Normal Operating Temperature Range | |
| TOPER Extended Temperature Range | |
| VDD Supply Voltage (Recommended DC Operating Conditions) | |
| VDDQ Supply Voltage for Output (Recommended DC Operating Conditions) | |
| VPP Supply Voltage for DRAM Activating (Recommended DC Operating Conditions) | |
| VREFCA(DC) Reference Voltage for ADD, CMD inputs | |
| VIHdiff Differential input high (DDR4-1600/1866/2133) | |
| VIHdiff Differential input high (DDR4-3200) | |
| tDVAC allowed time before ringback for CK (slew rate >4.0 V/ns, |VIH/Ldiff(AC)|=200mV) | |
| VIH(AC)_RESET AC Input High Voltage | |
| VIH(DC)_RESET DC Input High Voltage | |
| VIL(DC)_RESET DC Input Low Voltage | |
| VIL(AC)_RESET AC Input Low Voltage | |
| tPW_RESET RESET pulse width | |
| VIHDiff_DQS Differential Input High (DDR4-1600,1866,2133) | |
| VIHDiff_DQS Differential Input High (DDR4-3200) | |
| SRIdiff Differential Input Slew Rate for DQS (DDR4-1600/1866/2133) | |
| SRIdiff Differential Input Slew Rate for DQS (DDR4-2666/2933/3200) | |
| VOH(DC) DC output high measurement level | |
| VOM(DC) DC output mid measurement level | |
| VOL(DC) DC output low measurement level | |
| VOHdiff(AC) AC differential output high measurement level | |
| SRQse Single-ended output slew rate | |
| SRQdiff Differential output slew rate | |
| DDR4-1600K - CL-nRCD-nRP | |
| DDR4-1600K - tAA (Internal read command to first data) | |
| DDR4-1600K - tRCD (ACT to internal read or write delay time) | |
| DDR4-1600K - tRP (PRE command period) | |
| DDR4-1600K - tRAS (ACT to PRE command period) | |
| DDR4-1600K - tRC (ACT to ACT or REF command period) | |
| DDR4-1600K - Supported CL Settings | |
| DDR4-1600K - Supported CL Settings with read DBI | |
| DDR4-1600K - Supported CWL Settings | |
| DDR4-1866M - CL-nRCD-nRP | |
| DDR4-1866M - tAA | |
| DDR4-1866M - tRCD | |
| DDR4-1866M - tRP | |
| DDR4-1866M - tRAS | |
| DDR4-1866M - tRC | |
| DDR4-1866M - Supported CL Settings | |
| DDR4-1866M - Supported CL Settings with read DBI | |
| DDR4-1866M - Supported CWL Settings | |
| DDR4-2133P - CL-nRCD-nRP | |
| DDR4-2133P - tAA | |
| DDR4-2133P - tRCD | |
| DDR4-2133P - tRP | |
| DDR4-2133P - tRAS | |
| DDR4-2133P - tRC | |
| DDR4-2133P - Supported CL Settings | |
| DDR4-2133P - Supported CL Settings with read DBI | |
| DDR4-2133P - Supported CWL Settings | |
| DDR4-2400T - CL-nRCD-nRP | |
| DDR4-2400T - tAA | |
| DDR4-2400T - tRCD | |
| DDR4-2400T - tRP | |
| DDR4-2400T - tRAS | |
| DDR4-2400T - tRC | |
| DDR4-2400T - Supported CL Settings | |
| DDR4-2400T - Supported CL Settings with read DBI | |
| DDR4-2400T - Supported CWL Settings | |
| DDR4-2666V - CL-nRCD-nRP | |
| DDR4-2666V - tAA | |
| DDR4-2666V - tRCD | |
| DDR4-2666V - tRP | |
| DDR4-2666V - tRAS | |
| DDR4-2666V - tRC | |
| DDR4-2666V - Supported CL Settings | |
| DDR4-2666V - Supported CL Settings with read DBI | |
| DDR4-2666V - Supported CWL Settings | |
| DDR4-2933Y - CL-nRCD-nRP | |
| DDR4-2933Y - tAA | |
| DDR4-2933Y - tRCD | |
| DDR4-2933Y - tRP | |
| DDR4-2933Y - tRAS | |
| DDR4-2933Y - tRC | |
| DDR4-2933Y - Supported CL Settings | |
| DDR4-2933Y - Supported CL Settings with read DBI | |
| DDR4-2933Y - Supported CWL Settings | |
| DDR4-3200AA - CL-nRCD-nRP | |
| DDR4-3200AA - tAA | |
| DDR4-3200AA - tRCD | |
| DDR4-3200AA - tRP | |
| DDR4-3200AA - tRAS | |
| DDR4-3200AA - tRC | |
| DDR4-3200AA - Supported CL Settings | |
| DDR4-3200AA - Supported CL Settings with read DBI | |
| DDR4-3200AA - Supported CWL Settings | |
| Absolute Specification - VDDQ = VDD | |
| Absolute Specification - VPP | |
| Speed Bin Tables validity | |
| IDD specification note | |
| IDD4RB | |
| IDD4WB | |
| IPP5B | |
| Module configuration | |
| Dimensional units | |
| Default tolerance on all dimensions unless otherwise stated | |
| Module width (Front, overall) | |
| Module width (Front) | |
| Front edge dimension | |
| Front dimension | |
| Front dimension (key/notch region) | |
| Back view dimension | |
| Component on module | |
| Side view dimension (PCB thickness) | |
| Side view dimension (max height/thickness) | |
| Detail A dimension | |
| Detail of Contacts A, F dimension | |
| Detail of Contacts B dimension (pin reference) | |
| Detail of Contacts B dimension | |
| Detail of Contacts C dimension (pin reference) | |
| Detail of Contacts C dimension | |
| Keep-out area note | |
| Keep-out area dimension (max) | |
| Detail of Contacts D dimension | |
| Detail E / Detail of Contacts E dimension | |
| Detail of Contacts E dimension | |
| Detail E dimension | |
| Detail B dimension (pin reference) | |
| Detail C dimension (pin reference) | |
| Lower detail view dimension | |
| Corner radius callout | |
| Detail D/F dimension |
