Loading the catalog…
AC-212825002 (Ampere)
Blurred values are subscriber-only. Sign in to start a free trial — 2 full pages a day — or subscribe for unlimited access.
| Process Node | TSMC 7 nm FinFET |
|---|---|
| Memory Channels | 8 |
| Cores | 128 |
| Tdp W | 250 |
| L3 Cache Mb | 16 |
| Max Memory Capacity Tb | 4 |
| Socket | 4926-Pin Flip Chip Land Grid Array (FCLGA) |
| Product Name | Ampere Altra Max Rev A1 64-Bit Multi-Core Processor |
| Max Tdp W | |
| Ras Features |
| SKU | AC-212825002 |
|---|
| Product name | |
|---|---|
| Revision | |
| Architecture / data width | |
| Document Issue | |
| Document number |
| Maximum core frequency |
|---|
| L1 I-cache per core |
|---|
| L1 D-cache per core |
|---|
| L2 cache per core |
|---|
| System Level Cache (SLC) |
|---|
| SIMD |
|---|
| Interconnect |
|---|
| Memory ECC / RAS |
|---|
| Max DIMMs |
|---|
| Max memory per socket |
|---|
| Interrupt virtualization |
|---|
| I/O virtualization |
|---|
| PCIe lanes |
|---|
| PCIe controllers (ESM) |
|---|
| PCIe Gen4 x4 lanes (1P) |
|---|
| PCIe Gen4 x4 lanes (2P) |
|---|
| Multi-socket support |
|---|
| CCIX lanes |
|---|
| Architecture compliance |
|---|
| Advanced Power Management |
|---|
| Est. SPECrate® 2017_int_base |
|---|
| SPECrate benchmark SKU |
|---|
| Usage Power |
|---|
| Power envelope |
|---|
| Est. SPECrate® 2017_int_base throughput |
|---|
| Architecture compliance (SBSA / SBBR) |
|---|
| Generation |
|---|
| Processor Modules (PMDs) |
|---|
| Core architecture compliance |
|---|
| AArch32 support |
|---|
| Addressing |
|---|
| Core pipeline |
|---|
| SIMD pipes |
|---|
| Distributed home nodes / snoop filters |
|---|
| GIC compliance |
|---|
| L1 Data Cache |
|---|
| L1 Data TLB page sizes |
|---|
| L1 Instruction Cache |
|---|
| L1 Instruction TLB page sizes |
|---|
| L2 Cache |
|---|
| DSU mesh interface |
|---|
| L2 coherency |
|---|
| System Level Cache (SLC) size |
|---|
| SLC associativity |
|---|
| SLC data buses |
|---|
| GIC core support |
|---|
| Private Peripheral Interrupts (PPIs) |
|---|
| SGIs |
|---|
| ITS system |
|---|
| Interrupt priority values |
|---|
| SMMU architecture |
|---|
| Generic Timer counter frequency |
|---|
| Counter output width |
|---|
| Watchdog Timers |
|---|
| Memory controllers |
|---|
| DDR4 speed |
|---|
| DIMMs per channel |
|---|
| DRAM device support |
|---|
| DIMM type support |
|---|
| DDR4 RAS features |
|---|
| PCIe Gen4 lanes |
|---|
| PCIe max lanes (2P) |
|---|
| PCIe generations supported |
|---|
| PCIe networking support |
|---|
| SMMU version (PCIe) |
|---|
| PCIe MPS (x16/x8 root ports) |
|---|
| PCIe MPS (x4 root ports) |
|---|
| PCIe lanes (1P max) |
|---|
| PCIe lanes (2P max) |
|---|
| SMpro processor |
|---|
| SMpro max core frequency |
|---|
| SMpro local RAM |
|---|
| SMpro performance |
|---|
| SMpro I2C default frequency |
|---|
| PMpro processor |
|---|
| PMpro RAM |
|---|
| PMpro I2C capability |
|---|
| I2C controllers |
|---|
| I2C SMBus/PMBus capability |
|---|
| UART configurations |
|---|
| Timer frames |
|---|
| GPIOs |
|---|
| GPIs |
|---|
| JTAG debug interfaces |
|---|
| Package width |
|---|
| Package length |
|---|
| Processor typical weight |
|---|
| Package marking SKU ID |
|---|
| Pin assignment table scope |
|---|
