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AC-108025002 (Ampere)
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| Process Node | TSMC 7 nm FinFET |
|---|---|
| Memory Channels | 8 |
| Cores | 80 |
| Tdp W | 250 |
| L3 Cache Mb | 32 |
| Max Memory Capacity Tb | 4 |
| Socket | Coherent multi-socket support |
| Architecture | Arm® v8.2+ 64-bit |
| Product Name | Ampere Altra Rev A1 64-Bit Multi-Core Processor (Q80-30) |
| Max Tdp W | |
| Ras Features |
| Vendor | Ampere |
|---|---|
| SKU | AC-108025002 |
| Product name | |
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| Document Issue | |
| Document number | |
| Datasheet date | |
| Manufacturer address |
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| Maximum core frequency |
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| L1 I-cache per core |
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| L1 D-cache per core |
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| L2 cache per core |
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| System Level Cache (SLC) |
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| SIMD |
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| Interconnect |
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| Memory ECC / RAS |
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| Maximum DIMMs and capacity |
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| Interrupt virtualization |
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| I/O virtualization |
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| PCIe lanes |
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| PCIe configuration |
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| PCIe controllers (1P) |
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| PCIe controllers (2P) |
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| Multi-socket support |
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| CCIX lanes |
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| Architecture compliance |
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| Power management |
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| Est. SPECrate® 2017_int_base |
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| Usage Power |
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| Power envelope |
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| SPECrate® 2017_int_base throughput (estimated, family) |
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| Standards compliance |
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| Processor Modules (PMDs) |
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| Core execution |
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| SIMD pipes |
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| Addressing |
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| Architecture compliance (core) |
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| AArch32 support |
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| Mesh home nodes |
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| GIC compliance |
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| L1 Data Cache |
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| L1 Data TLB page sizes |
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| L1 Instruction Cache |
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| L1 Instruction TLB page sizes |
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| L2 Cache |
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| L2 DSU mesh interface |
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| L2 coherency |
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| SLC size |
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| SLC associativity |
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| SLC data buses |
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| GIC compliance (version) |
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| GIC cores supported |
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| Private Peripheral Interrupts (PPIs) |
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| SGIs |
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| ITS count |
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| Interrupt priority values |
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| SMMU version |
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| Generic Timer counter frequency |
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| Generic Timer counter bits |
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| Watchdog Timers |
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| DDR4 memory channels |
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| DIMMs per channel (DPC) |
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| DRAM device support |
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| DIMM type support |
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| DRAM device technology support |
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| Memory interleave |
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| PCIe controller |
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| PCIe x16 controller features |
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| PCIe specification compliance |
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| PCIe PHY rating |
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| SMMU version (PCIe section) |
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| 2P PCIe controllers / lanes |
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| Maximum Payload Size (MPS) — x16, x8 root ports |
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| Maximum Payload Size (MPS) — x4, x2 root ports |
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| SMpro I2C frequency |
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| SMpro processor |
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| SMpro maximum frequency |
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| SMpro RAM |
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| SMpro AHB-Lite processor interfaces |
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| PMpro processor |
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| PMpro RAM |
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| PMpro I2C |
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| PMpro power management features |
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| I2C controllers (low-speed) |
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| QSPI configurations |
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| PL011 UART configurations |
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| Timers (low-speed) |
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| GPIOs |
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| GPIs |
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| JTAG debug interfaces |
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| Package type |
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| Package dimensions |
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| Pin count |
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| Silicon revision |
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| Package marking — product name line |
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| Package marking — ordering part number |
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| Country of origin |
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| Typical weight (mass) |
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